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參數(shù)資料
| 型號(hào)： | NB7VPQ16MMNG |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 16/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CML PRE-EMPH DRIVER 16QFN |
| 標(biāo)準(zhǔn)包裝： | 123 |
| 邏輯類(lèi)型： | CML 驅(qū)動(dòng)器，帶可選均衡器接收器 |
| 電源電壓： | 1.71 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 管件 |
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NB7VPQ16M
http://onsemi.com
9
APPLICATION INFORMATION
Data Inputs
The differential IN/IN inputs of the NB7VPQ16M can
accept LVPECL, CML, and LVDS signal levels. The
limitations for a differential input signal (LVDS, LVPECL,
or CML) is a minimum input swing of 100 mV
(singleended measurement). Within this condition, the
input HIGH voltage, VIH, can range from VCC down to
1.1 V. Example interfaces are illustrated in Figure 17.
Serial Data Interface
The Serial Data Interface (SDI) logic is implemented with
a 5bit shift register scheme. The register shifts once per
rising edge of the SCLKIN input. The serial data input SDIN
must meet setup and hold timing as specified in the AC table.
The configuration latches will capture the value of the shift
register on the LowtoHigh edge of the SLOAD input. The
most significant bit (MSB) is loaded first. See the
programming timing diagram for more information.
SDIN / SCLKIN
SDIN is the Serial Data input pin; SCLKIN is the Serial
Clock input pin.
SLOAD
The SLOAD pin performs the DAC latch function. When
LOW or left open, the DAC latch will pass the shift register
outputs to the input of the DAC and the EQualizer ENable
bit (EQEN). On the LowtoHIGH transition of SLOAD,
the input to the 4bit DAC is locked to the state prior to when
SLOAD went HIGH, and will set the EQualizer ENable bit.
The DAC does not get programmed until SLOAD goes
HIGH. The SLOAD pin must remain in a HIGH state to
maintain the DAC PreEmphasis and the EQEN settings. A
LOW or open state resets the DAC to 0 db PreEmphasis
setting and disables the EQEN bit, regardless of SDIN and
SCLKIN values. The SLOAD function is asynchronous.
Figure 11. Timing Diagram for Single Channel
D3
D2
D1
D0
EQEN
123
456
789
10
11
12
1
2
345
6
7
89
10
11
/////
D3
D2
D1
D0
EQEN
/////
5 Clock
SCLKIN to SDOUT
SDIN
SCLKIN
SLOAD
SDOUT
SCLKOUT
tPWMIN
PreEmphasis Selection
The PreEmphasis buffer is controlled using a serial bus
via the SDIN (Serial Data In) and SCLKIN (Serial Clock In)
control inputs and contains circuitry which provides sixteen
programmable preemphasis levels to control the output
compensation. The 4bits (D3:D0) digitally select 0 dB
through 12 dB of PreEmphasis compensation (see
Table 1). The default state at startup is PE = 0 dB.
EQualization ENable (EQEN)
The EQualizer ENable (EQEN) allows for enabling the
Equalizer function. The control of the Equalizer function is
realized by setting the 5th bit, EQEN, of the 5bit serial data.
When EQEN is set Low (or open), the IN/IN inputs bypass
the Equalizer. When EQEN is set High, the IN/IN inputs
flow through the Equalizer. The default state at startup is
EQEN = LOW.
Q/Q Outputs
The differential outputs of the NB7VPQ16M, Q and Q,
utilize Common Mode Logic (CML) architecture. The
outputs are designed to drive differential transmission lines
with nominal 50
W characteristic impedance. External
termination with a 50
W resistor to VCC is recommended.
Alternatively, 100
W linetoline termination is also
acceptable.
Power Supply Bypass information
A clean power supply will optimize the performance of
the NB7VPQ16M. The device provides separate VCCD and
VCC power supply pins for the digital circuitry and CML
outputs. Placing a 0.01
mF to 0.1 mF bypass capacitor on
each VCC and VCCD Pin to ground will help ensure a noise
free power supply. The purpose of this design technique is
to isolate the CMOS digital switching noise from the high
speed input/output path.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB7VPQ16MMNGM | 制造商:Rochester Electronics LLC 功能描述: 制造商:ON Semiconductor 功能描述: |
| NB7VPQ16MMNHTBG | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 EQU/PREEMP SNGLE CHN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類(lèi)型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| NB7VPQ16MMNTXG | 功能描述:緩沖器和線路驅(qū)動(dòng)器 EQU/PREEMP SNGL CHAN RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| NB7VQ1006M | 制造商:ONSEMI 制造商全稱(chēng):ON Semiconductor 功能描述:1.8V / 2.5V 10Gbps Equalizer Receiver with 1:6 Differential CML Outputs |
| NB7VQ1006MMNG | 功能描述:IC EQUALIZER RECEIVER 24-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 邏輯 - 專(zhuān)用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類(lèi)型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
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