10.VCMR min varies 1:1 with GND, VCM" />
參數(shù)資料
型號: NB7V32MMNG
廠商: ON Semiconductor
文件頁數(shù): 5/9頁
文件大?。?/td> 0K
描述: IC CLOCK DIVIDER 1.8/2.5V 16-QFN
標(biāo)準(zhǔn)包裝: 123
系列: GigaComm™
類型: 時鐘除法器
PLL:
輸入: CML,LVDS,LVPECL
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 10GHz
除法器/乘法器: 是/無
電源電壓: 1.71 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 管件
NB7V32M
http://onsemi.com
5
10.VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
Table 6. AC CHARACTERISTICS VCC = 1.71 V to 2.625 V; GND = 0 V; TA = 40°C to 85°C (Note 11)
Symbol
Characteristic
Min
Typ
Max
Unit
fMAX
Maximum Input Clock Frequency
10
GHz
VOUTPP Output Voltage Amplitude (@ VINPPmin)
fin ≤ 10GHz
(Note 12) (Figure 3)
280
400
mV
tPLH,
tPHL
Propagation Delay to Differential Outputs, @
1 GHz, measured at differential crosspoint
CLK/CLK to Q, Q
R to Q, Q
150
200
275
ps
tPLH TC Propagation Delay Temperature Coefficient
50
Dfs/°C
tskew
Duty Cycle Skew (Note 13)
Device Device skew (tpdmax – tpdmin)
20
50
ps
tRR
Reset Recovery (See Figure 11)
300
135
tPW
Minimum Pulse Width R
500
200
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 10 GHz
45
50
55
%
tJITTER
RJ – Output Random Jitter (Note 14) fin v 10 GHz
0.2
0.8
ps
RMS
VINPP
Input Voltage Swing (Differential Configuration) (Figure 10) (Note 15)
100
1200
mV
tr, tf
Output Rise/Fall Times @ 1 GHz (20% 80%), Q, Q
35
60
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 1 GHz, VINPPmin, 50% dutycycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps
(20% 80%).
12.Output voltage swing is a singleended measurement operating in differential mode.
13.Duty cycle skew is defined only for differential operation when the delays are measured from crosspoint of the inputs to the crosspoint
of the outputs. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+ @ 1 GHz. Skew
is measured between outputs under identical transitions and conditions.
14.Additive RMS jitter with 50% duty cycle clock signal.
15.Input voltage swing is a singleended measurement operating in differential mode.
Figure 3. CLOCK Output Voltage Amplitude
(VOUTPP) vs. Input Frequency (fin) at Ambient
Temperature (Typ)
fin, Clock Input Frequency (GHz)
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
500
450
400
350
300
200
Q AMP (mV)
Figure 4. Input Structure
50 W
CLK
VCC
VTCLK
250
02
4
6
8
10
CLK
RC
I
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