Table 5. AC CHARACTERISTICS (VCC = 2" />
參數(shù)資料
型號(hào): NB7L14MMN
廠商: ON Semiconductor
文件頁(yè)數(shù): 7/11頁(yè)
文件大?。?/td> 0K
描述: IC CLK/DTA BUF TRNSLA 1:4 16-QFN
產(chǎn)品變化通告: LTB Notification 06/Feb/2008
標(biāo)準(zhǔn)包裝: 123
類(lèi)型: 扇出緩沖器(分配),變換器,數(shù)據(jù)
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
輸入: CML,LVCMOS,LVDS,LVPECL,LVTTL
輸出: CML
頻率 - 最大: 8GHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 管件
NB7L14M
http://onsemi.com
5
Table 5. AC CHARACTERISTICS (VCC = 2.375 V to 3.465 V, VEE = 0 V; Note 11)
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOUTPP Output Voltage Amplitude (@VINPPmin)fin ≤ 6 GHz
(See Figure 4)
fin ≤ 8 GHz
280
125
400
300
280
125
400
300
280
125
400
300
mV
fdata
Maximum Operating Data Rate
10
12
10
12
10
12
Gb/s
tPLH,
tPHL
Propagation Delay to Output Differential
70
110
150
70
110
150
70
110
150
ps
tSKEW
Duty Cycle Skew (Note 12)
WithinDevice Skew
DevicetoDevice Skew (Note 13)
2.0
6.0
20
5.0
15
50
2.0
6.0
20
5.0
15
50
2.0
6.0
20
5.0
15
50
ps
tJITTER
RMS Random Clock Jitter (Note 14)
fin = 6 GHz
fin = 8 GHz
Peak/Peak Data Dependent Jitter fin = 2.488 Gb/s
(Note 15)
fdata = 5 Gb/s
fdata = 10 Gb/s
0.2
2.0
5.0
6.0
0.5
5.0
8.0
10
0.2
2.0
5.0
6.0
0.5
5.0
8.0
10
0.2
2.0
5.0
6.0
0.5
5.0
8.0
10
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 16)
75
400
2500
75
400
2500
75
400
2500
mV
tr
tf
Output Rise/Fall Times @ 1 GHz
Q, Q
(20% 80%)
30
60
30
60
30
60
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured by forcing VINPP (TYP) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC.
Input edge rates 40 ps (20% 80%).
12.Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+ @1 GHz.
13.Device to device skew is measured between outputs under identical transition @ 1 GHz.
14.Additive RMS jitter with 50% duty cycle clock signal at 10 GHz.
15.Additive peaktopeak data dependent jitter with input NRZ data at PRBS 2^231.
16.VINPP (MAX) cannot exceed VCC VEE. Input voltage swing is a singleended measurement operating in differential mode.
INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) at Ambient Temperature (Typical)
(VINPP = 400 mV)
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
450
300
250
200
150
100
50
0
12
11
10
9
8
7
6
5
4
3
2
1
350
400
VCC = 3.3 V
VCC = 2.5 V
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