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參數(shù)資料
| 型號： | NB6VQ572MMNR4G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK MUX TRANSLA 4:2 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | ECLinPS MAX™ |
| 類型： | 多路復(fù)用器，變換器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVDS，LVPECL |
| 輸出： | CML |
| 頻率 - 最大： | 5GHz |
| 電源電壓： | 1.71 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 帶卷 (TR) |
NB6VQ572M
http://onsemi.com
3
Table 2. PIN DESCRIPTION
Pin Number
Pin Name
I/O
Pin Description
1, 4
5, 8
25, 28
29, 32
IN0, IN0
IN1, IN1
IN2, IN2
IN3, IN3
LVPECL, CML,
LVDS Input
Noninverted, Inverted, Differential Clock or Data Inputs
2, 6
26, 30
VT0, VT1
VT2, VT3
Internal 100 W Centertapped Termination Pin for INx / INx
15
18
SEL0
SEL1
LVTTL/LVCMOS
Input
Input Select pins, default HIGH when left open through a 94 kW pullup resistor. Input
14, 19
NC
No Connect
10, 13, 16
17, 20, 23
VCC
Positive Supply Voltage.
11, 12
21, 22
Q0, Q0
Q1, Q1
CML Output
Inverted, Noninverted Differential Outputs.
9, 24
GND
Negative Supply Voltage
3
7
27
31
VREFAC0
VREFAC1
VREFAC2
VREFAC3
Output Voltage Reference for CapacitorCoupled Inputs
EP
The Exposed Pad (EP) on the QFN32 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be at-
tached to a heatsinking conduit. The pad is electrically connected to the die, and
must be electrically connected to GND.
1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or
left open, and if no signal is applied on INx/INx input, then the device will be susceptible to selfoscillation.
2. All VCC, and GND pins must be externally connected to a power supply for proper operation.
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