Table 6. AC CHARACTERISTICS VCC = " />
參數(shù)資料
型號(hào): NB6VQ572MMNG
廠商: ON Semiconductor
文件頁數(shù): 8/11頁
文件大小: 0K
描述: IC CLOCK MUX TRANSLA 4:2 32-QFN
標(biāo)準(zhǔn)包裝: 74
系列: ECLinPS MAX™
類型: 多路復(fù)用器,變換器
電路數(shù): 1
比率 - 輸入:輸出: 4:2
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: CML
頻率 - 最大: 5GHz
電源電壓: 1.71 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN(5x5)
包裝: 管件
NB6VQ572M
http://onsemi.com
6
Table 6. AC CHARACTERISTICS VCC = 1.71 V to 2.625 V, GND = 0 V, TA = 40°C to +85°C (Note 11)
Symbol
Characteristic
Min
Typ
Max
Unit
fMAX
Maximum Input Clock Frequency
VOUT w 250 mV
5
6
GHz
fDATAMAX
Maximum Operating Data Rate
NRZ, (PRBS23)
6.5
8
Gbps
fSEL
Maximum Toggle Frequency, SELx
4
10
MHz
VOUTPP
Output Voltage Amplitude (@ VINPPmin) (Note 12) (Figure 12)
fin ≤ 5 GHz
250
400
mV
tPLH,
tPHL
Propagation Delay to Differential
Outputs Measured at Differential
Crosspoint
@ 1 GHz INx/INx to Qx/Qx
@ 50 MHz SELx to Qx
100
175
7
250
20
ps
ns
tPD Tempco
Differential Propagation Delay Temperature Coefficient
50
Dfs/°C
tskew
Output Output skew (within device) (Note 13)
Device Device skew (tpdmax tpdmin)
0
30
15
100
ps
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
fIN v 5 GHz
45
50
55
%
FN
Phase Noise, fin = 1 GHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
135
136
149
150
151
dBc
t FN
Integrated Phase Jitter (Figure TBD) fin = 1 GHz, 12 kHz 20 MHz
Offset (RMS)
35
fs
tJITTER
Random Clock Jitter, RJ (Note 14)
fin ≤ 5 GHz
Deterministic Jitter, DJ (Note 15)
fin ≤ 6.5 Gbps (12” FR4)
0.2
0.8
10
ps RMS
ps pkpk
Crosstalk Induced Jitter (Adjacent Channel) (Note 17)
0.7
ps RMS
VINPP
Input Voltage Swing (Differential Configuration) (Note 16)
100
1200
mV
tr,, tf
Output Rise/Falltimes @ 1 GHz; (20% 80%), VIN = 400 mV Qx, Qx
25
45
65
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 100 mVpkpk source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates
40 ps (20% 80%).
12.Output voltage swing is a singleended measurement operating in differential mode.
13.Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from crosspoint of the inputs to the crosspoint of the outputs.
14.Additive RMS jitter with 50% duty cycle clock signal.
15.Additive PeaktoPeak data dependent jitter with input NRZ data at PRBS23.
16.Input voltage swing is a singleended measurement operating in differential mode.
17.Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
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