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參數(shù)資料
| 型號(hào)： | NB6N14SMNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFFER TRANSLA 1:4 16-QFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | AnyLevel™ ECLinPS MAX™ |
| 類型： | 扇出緩沖器（分配），變換器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVDS，LVPECL |
| 輸出： | LVDS |
| 頻率 - 最大： | 2GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 帶卷 (TR) |
NB6N14S
http://onsemi.com
2
Figure 3. NB6N14S Pinout, 16pin QFN (Top View)
Q3
VCC
EN
GND
IN
VT
VREF_AC
IN
Q1
Q2
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB6N14S
Exposed Pad (EP)
Q0
VCC
IN
EN
Q
01
1
0
10
1
x
0
0 (Note 1)
1. On next transition of the input signal (IN).
Table 1. TRUTH TABLE
Q
1
0
1 (Note 1)
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
Q1
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2
Q1
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
3
Q2
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
4
Q2
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5
Q3
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
6
Q3
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
7
VCC
Positive Supply Voltage.
8
EN
LVTTL / LVCMOS Input
Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb
outputs will go HIGH on the next negative transition of IN input. The internal
DFF register is clocked on the falling edge of IN input; see Figure 23. The EN
pin has an internal pullup resistor and defaults HIGH when left open.
9
IN
LVPECL, CML, LVDS
Inverted Differential Input
10
VREF_AC
LVPECL Output
The VREF_AC reference output can be used to rebias capacitorcoupled
differential or singleended input signals. For the capacitorcoupled IN and/or
INb inputs, VREF_AC should be connected to the VT pin and bypassed to
ground with a 0.01 mF capacitor.
11
VT
LVPECL Output
Internal 100 W Centertapped Termination Pin for IN and IN
12
IN
LVPECL, CML, LVDS
Noninverted Differential Input. (Note 2)
13
GND
Negative Supply Voltage.
14
VCC
Positive Supply Voltage.
15
Q0
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
16
Q0
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heatsinking conduit. The pad is not electrically connected to the
die, but is recommended to be electrically and thermally connected to GND on
the PC board.
2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied
on IN/IN inputs, then the device will be susceptible to selfoscillation.
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| NB6N239S | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT ±1/2/4/8, ±2/4/8/16 Clock Divider |
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| NB6N239SMNEVB | 功能描述:BOARD EVAL BBG NB6N239SMN RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| NB6N239SMNG | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3V 3GHz LVDS OUT Clock Divider RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| NB6N239SMNR2 | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3V 3GHz LVDS OUT RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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