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參數資料
| 型號： | NB6LQ572MNG |
| 廠商： | ON Semiconductor |
| 文件頁數： | 7/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK MUX TRANSLA 4:2 32-QFN |
| 標準包裝： | 74 |
| 系列： | ECLinPS MAX™ |
| 類型： | 多路復用器，變換器 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 4:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVDS，LVPECL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 5GHz |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-QFN（5x5） |
| 包裝： | 管件 |
NB6LQ572
http://onsemi.com
6
Symbol
Characteristic
Min
Typ
Max
Unit
fMAX
Maximum Input Clock Frequency
VOUT w 450 mV
5
6
GHz
fDATAMAX
Maximum Operating Data Rate
NRZ, (PRBS23)
6.5
8
Gbps
fSEL
Maximum Toggle Frequency, SELx
4
10
MHz
VOUTPP
450
800
mV
tPLH,
tPHL
Propagation Delay to Differential Outputs
Measured at Differential Crosspoint
INx/INx to Qx/Qx @1 GHz
@ 50 MHz SELn to Qx
100
175
5
250
10
ps
ns
tPD Tempco
Differential Propagation Delay Temperature Coefficient
100
Dfs/°C
tskew
Output – Output skew (within device) (Note 13)
Device – Device skew (tpdmax – tpdmin)
0
30
15
100
ps
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
fin = 1 GHz
45
50
55
%
FN
Phase Noise, fin = 1 GHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
134
136
149
150
dBc
t FN
Integrated Phase Jitter (Figure 1) fin = 1GHz, 12 kHz 20 MHz Offset (RMS)
35
fs
tJITTER
Random Clock Jitter, RJ(RMS), (Note 14)
Deterministic Jitter, DJ (Note 15)
0.2
0.8
10
ps
Crosstalk Induced Jitter (Adjacent Channel) (Note 16)
0.7
psRMS
VINPP
Input Voltage Swing (Differential Configuration) (Note 17)
100
1200
mV
tr,, tf
Output Rise/Fall Times @ 1 GHz; (20% 80%), Qx, Qx
25
50
75
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a VINPPmin source, 50% duty cycle clock source. All output loading with external 50 W to VCC 2 V. Input edge rates 40 ps
(20% 80%).
12.Output voltage swing is a singleended measurement operating in differential mode.
13.Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from crosspoint of the inputs to the crosspoint of the outputs.
14.Additive RMS jitter with 50% duty cycle clock signal.
15.Additive PeaktoPeak data dependent jitter with input NRZ data at PRBS23.
16.Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
17.Input voltage swing is a singleended measurement operating in differential mode.
900
850
800
750
700
650
600
550
500
0
fin, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Clock Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical)
8.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
Q AMP (mV)
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