- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9303 > NB6L295MMNG (ON Semiconductor)IC DELAY LINE 511TAP 24-QFN PDF資料下載
參數(shù)資料
| 型號： | NB6L295MMNG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 511TAP 24-QFN |
| 標準包裝： | 92 |
| 標片/步級數(shù)： | 512 |
| 功能： | 多重，可編程 |
| 延遲到第一抽頭： | 3.2ns，6.2ns |
| 接頭增量： | 11ps |
| 可用的總延遲： | 3.2ns ~ 8.5ns，6.2ns ~ 16.6ns |
| 獨立延遲數(shù)： | 2 |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN（4x4） |
| 包裝： | 管件 |
| 其它名稱： | NB6L295MMNG-ND NB6L295MMNGOS |
NB6L295M
http://onsemi.com
8
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL
PSEL
Figure 7. Serial Data Interface, Shift Register, Data Latch, Programmable Delay Channels
Load Cycle Required for Each Channel
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
01
PD1 Latch
PD0 Latch
PD0 Delay
PD1 Delay
SLOAD
Q1/Q1
Q0/Q0
SDATA
SCLK
11Bit Shift Register
MSEL
Serial Data Interface Loading
Loading the device through the 3 input Serial Data Interface (SDI) is accomplished by sending data into the SDIN pin by
using the SCLK input pin and latching the data with the SLOAD input pin. The 11bit SHIFT REGISTER shifts once per rising
edge of the SCLK input. The serial input SDIN must meet setup and hold timing as specified in the AC Characteristics section
of this document for each bit and clock pulse. The SLOAD line loads the value of the shift register on a LOWtoHIGH edge
transition (transparent state) into a data Latch register and latches the data with a subsequent HIGHtoLOW edge transition.
Further changes in SDIN or SCLK are not recognized by the latched register. The internal multiplexer states are set by the PSEL
and MSEL bits in the SHIFT register. Figure 6 shows the timing diagram of a typical load sequence.
Input EN should be LOW (enabled) prior to SDI programming, then pulled HIGH (disabled) during programming. After
programming, the EN should be returned LOW (enabled) for functional delay operation.
The disabling of EN (HIGH) forces Qx LOW and Qx HIGH and is included during programming to prevent (or mask out)
any potential run pulses or extended pulses which might occur in the internal delay gates programming switching, but it is not
required for programming.
D4
D8
D7
Figure 8. SDI Programming Cycle Timing Diagram (Load Cycle 1 of 2)
SDIN
SCLK
SLOAD
EN
MSB
PSEL MSEL
D0
D1
D2
D3
D5
D6
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
ts SDIN to
SCLK
th SDIN to SCLK
ts SCLK to SLOAD
tH SCLK to SLOAD
EN to SDIN
LSB
EN to SLOAD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MS27466E25B35SB | CONN RCPT 128POS WALL MNT W/SCKT |
| GTC01R-10SL-3P | CONN RCPT 3POS INLINE W/PINS |
| AD5248BRM10-RL7 | IC DGTL POT DUAL 10K I2C 10-MSOP |
| MC100EP195MNG | IC DELAY LINE 1024TAP 32-QFN |
| AD5170BRM50-RL7 | IC DGTL POT 50K 256POS 10MSOP TR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB6L295MMNGEVB | 功能描述:電源管理IC開發(fā)工具 EVAL BOARD RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| NB6L295MMNTXG | 功能描述:延遲線/計時元素 CML DUAL PROG DELAY RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| NB6L295MNG | 功能描述:延遲線/計時元素 LVPECL DUAL PRG DLAY RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| NB6L295MNGEVB | 功能描述:電源管理IC開發(fā)工具 NB6L295 EVAL BOARD RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| NB6L295MNTXG | 功能描述:延遲線/計時元素 LVPECL DUAL PRG DLAY RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。