Table 6. AC CHARACTERISTICS VCC = 2." />
參數(shù)資料
型號: NB6L14SMNTXG
廠商: ON Semiconductor
文件頁數(shù): 7/11頁
文件大?。?/td> 0K
描述: IC CLK BUFFER TRANSLA 1:4 16-QFN
標準包裝: 3,000
系列: AnyLevel™
類型: 扇出緩沖器(分配),變換器
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
輸入: CML,HSCL,LVDS,LVPECL
輸出: LVDS
頻率 - 最大: 2GHz
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應商設備封裝: 16-QFN(3x3)
包裝: 帶卷 (TR)
NB6L14S
http://onsemi.com
5
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 2.625 V, GND = 0 V; (Note 12)
Symbol
Characteristic
40°C to +85°C
Unit
Min
Typ
Max
finMax
Maximum Input Clock Frequency
2.0
GHz
VOUTPP Output Voltage Amplitude (@ VINPPmin)fin ≤ 1.0 GHz
(Figure 4)
fin= 1.5 GHz
fin= 2.0 GHz
220
200
170
350
300
270
mV
fDATA
Maximum Operating Data Rate
2.5
Gb/s
tPLH,
tPHL
Differential Input to Differential Output, IN to Q
Propagation Delay @ 100 MHz
300
450
600
ps
ts
th
Setup Time
EN to IN/IN
Hold Time
300
500
20
tSKEW
Within Device Skew (Note 17)
DevicetoDevice Skew (Note 16)
5
30
20
200
ps
tJITTER
RMS Random Clock Jitter (Note 14)
fin = 2.0 GHz
Deterministic Jitter (Note 15)
fDATA v 2.488 Gb/s
0.5
5.0
0.8
20
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 13)
100
VCCGND
mV
tr
tf
Output Rise/Fall Times @ 250 MHz
Q, Q
(20% 80%)
70
150
225
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12.Measured by forcing VINPPmin with 50% duty cycle clock source and VCC 1400 mV offset. All loading with an external RL = 100 W. Input
edge rates 150 ps (20%80%). See Figure 20.
13.Input voltage swing is a singleended measurement operating in differential mode.
14.RMS jitter with 50% Duty Cycle clock signal at 750 MHz.
15.Deterministic jitter with input NRZ data at PRBS 2231 and K28.5.
16.Skew is measured between outputs under identical transition @ 250 MHz.
17.The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 2.5 V)
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
0
50
100
150
200
250
300
350
400
0.5
1
1.5
2
2.5
3
0
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