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參數(shù)資料
型號(hào): NB6L11DTR2
廠商: ON Semiconductor
文件頁(yè)數(shù): 6/13頁(yè)
文件大?。?/td> 0K
描述: IC CLK BUFFER TRANSLA 1:2 8TSSOP
產(chǎn)品變化通告: Product Discontinuation 20/Aug/2008
標(biāo)準(zhǔn)包裝: 2,500
類型: 扇出緩沖器(分配),變換器
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
輸入: CML,LVCMOS,LVDS,LVNECL,LVPECL,LVTTL
輸出: ECL
頻率 - 最大: 6GHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 帶卷 (TR)
NB6L11
http://onsemi.com
2
1
2
3
4
5
6
7
8
D
VEE
VCC
Figure 1. Pinout (Top View) and Logic Diagram
Q0
D
Q1
Q0
R2
R1
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default State
Description
1
Q0
ECL Output
Noninverted differential clock/data output 0. Typically termin-
ated with 50 W Resistor to VTT = VCC 2 V.
2
Q0
ECL Output
Inverted differential clock/data output 0. Typically terminated with
50 W resistor to VTT = VCC 2 V.
3
Q1
ECL Output
Noninverted differential clock/data output 1. Typically termin-
ated with 50 W resistor to VTT = VCC 2 V.
4
Q1
ECL Output
Inverted differential clock/data output 1. Typically terminated with
50 W resistor to VTT = VCC 2 V.
5
VEE
Negative power supply voltage
6
D
LVDS, CML, LVPECL, LVNECL,
LVCMOS, LVTTL Input
HIGH
Inverted differential clock/data input. Internal 37.5 kW to VCC and
75 kW to VEE.
7
D
LVDS, CML, LVPECL, LVNECL,
LVCMOS, LVTTL Input
LOW
Noninverted differential clock/data input. Internal 75 kW to VCC
and 37.5 kW to VEE.
8
VCC
Positive power supply voltage
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Resistor R1
37.5 kW
Internal Input Resistor R2
75 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 1 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
PbFree Pkg
SOIC8
TSSOP8
Level 1
Level 3
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V0 @ 0.125 in
Transistor Count
167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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