Table 6. AC CHARACTERISTICS VCC = 2" />
參數(shù)資料
型號: NB6HQ14MMNG
廠商: ON Semiconductor
文件頁數(shù): 8/11頁
文件大小: 0K
描述: IC CLK BUFF MUX 1:4 5GHZ 16-QFN
標(biāo)準(zhǔn)包裝: 123
系列: ECLinPS MAX™
類型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: CML
頻率 - 最大: 5GHz
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 管件
NB6HQ14M
http://onsemi.com
6
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 2.625 V; VCCO = 1.71 V to 2.625 V; GND = 0 V; TA = 40°C to 85°C (Note 11)
Symbol
Characteristic
Min
Typ
Max
Unit
fMAX
Maximum Input Clock Frequency;
VOUT w 200 mV
5
7
GHz
fDATAMAX
Maximum Operating Data Rate (PRBS23)
6.5
10
Gbps
VOUTPP
Output Voltage Amplitude, EQEN = 0 or 1 (Note 15)
fin ≤ 5 GHz
(See Figures 3 and 10)
200
400
mV
tPLH,
tPHL
Propagation Delay, EQEN = 0 or 1
IN to Q
150
220
275
ps
tSKEW
Duty Cycle Skew (Note 12)
Output – Output Within Device Skew
Device to Device Skew
3
10
15
50
ps
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
fin = 1 GHz
45
50
55
%
FN
Phase Noise, fin = 1 GHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
132
135
145
146
147
148
dBc
t FN
Integrated Phase Jitter fin = 1 GHz, 12 kHz 20 MHz
Offset (RMS)
50
fs
tJITTER
RMS Random Clock Jitter (Note 13)
fin v 5 GHz
PeaktoPeak Data Dependent Jitter (Note 14)
fin v 3.0 Gb/s
EQEN = 0 (v 3” FR4)
EQEN = 1 (12” FR4)
0.2
0.8
15
10
ps rms
ps pkpk
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
100
1200
mV
tr
tf
Output Rise/Fall Times @ 1.0 GHz
Qx, Qx
(20% 80%)
15
30
60
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured by forcing VINPP min from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCCO. Input edge rates 40
ps (20% 80%).
12.Skew is measured between outputs under identical transitions and conditions @ 0.5 GHz. Duty cycle skew is measured between differential
outputs using the deviations of the sum of Tpw and Tpw+ @ 0.5 GHz.
13.Additive RMS jitter with 50% duty cycle clock signal.
14.Additive peaktopeak data dependent jitter with input NRZ data at PRBS23. For applications requiring equalization, the vertical eye height
is also a critical figure of merit. See Figure 4 for equalized eye height versus data rate.
15.Input and output voltage swings are singleended measurements operating in a differential mode.
600
500
400
300
200
100
0
01
2
7
6
5
34
Figure 3. CLOCK Output Voltage Amplitude (VOUTPP) vs.
Input Frequency (fin) at Ambient Temperature (Typical)
fin, CLOCK INPUT FREQUENCY (GHz)
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
Q AMP (mV)
8
Figure 4. NB6HQ14M Eye Height vs. Data
Rate
0
50
100
150
200
250
300
350
400
02
4
6
8
13
4
5
7
DATE RATE (Gbps)
EYE
HEIGHT
(mV)
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