- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363197 > NB4N855SMR4 (ON SEMICONDUCTOR) 3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator PDF資料下載
參數(shù)資料
| 型號(hào)： | NB4N855SMR4 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 其它接口 |
| 英文描述： | 3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PDSO10 |
| 封裝： | MICRO, 10 PIN |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 133K |
| 代理商： | NB4N855SMR4 |
Semiconductor Components Industries, LLC, 2005
June, 2005 Rev. 0
1
Publication Order Number:
NB4N855S/D
NB4N855S
3.3 V, 1.5 Gb/s Dual
AnyLevel
to LVDS
Receiver/Driver/Buffer/
Translator
Description
NB4N855S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevel
TM
input signal (LVPECL, CML,
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the
distance, noise immunity of the system design, and transmission line
media, this device will receive, drive or translate data or clock signals
up to 1.5 Gb/s or 1.0 GHz, respectively. This device is pinforpin
plug in compatible to the SY55855V in a 3.3 V applications.
The NB4N855S has a wide input common mode range of
GND + 50 mV to V
CC
50 mV. This feature is ideal for translating
differential or singleended data or clock signals to 350 mV typical
LVDS output levels.
The device is offered in a small 10 lead MSOP package. NB4N855S
is targeted for data, wireless and telecom applications as well as high
speed logic interface where jitter and package size are main
requirements.
Application notes, models, and support documentation are available
at www.onsemi.com.
Features
Guaranteed Input Clock Frequency up to 1.0 GHz
Guaranteed Input Data Rate up to 1.5 Gb/s
490 ps Maximum Propagation Delay
1.0 ps Maximum RMS Jitter
180 ps Maximum Rise/Fall Times
Single Power Supply; V
CC
= 3.3 V
±
10%
Temperature Compensated TIA/EIA644 Compliant LVDS Outputs
GND + 50 mV to V
CC
50 mV V
CMR
Range
Figure 1. Typical Output Waveform at 1.5 Gb/s with K28.5
(V
INPP
= 100 mV, Input Signal DDJ = 24 ps)
Device DDJ = 7 ps
TIME (133 ps/div)
V
(
A
Y
W
= Assembly Location
= Year
= Work Week
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
Micro 10
M SUFFIX
CASE 846B
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
Q0
Q0
Functional Block Diagram
D0
Q1
Q1
D0
D1
D1
1
10
1
855S
AYW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NB4N855SMR4G | 3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator |
| NB6L11M | 2.5V / 3.3V 1:2 Differential CML Fanout Buffer(2.5V/3.3V 1:2 差分CML輸出緩沖器) |
| NB6L16 | 2.5V/3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/Driver/Translator Buffer(2.5V/3.3V多級(jí)輸入到差分LVPECL/LVNECL時(shí)鐘或數(shù)據(jù)輸出接收器/驅(qū)動(dòng)器/轉(zhuǎn)換器/緩沖器) |
| NB6L239MNR2 | 2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT ±1/2/4/8, ±2/4/8/16 Clock Divider |
| NB6L239 | 2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT ±1/2/4/8, ±2/4/8/16 Clock Divider |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB4N855SMR4G | 功能描述:轉(zhuǎn)換 - 電壓電平 3.3V Dual Translator RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| NB50SI/12-C-D | 制造商:Martek Power Inc 功能描述:50W 12V OUT 28V IN DC/DC - Bulk |
| NB50SI/15-C-D | 制造商:Martek Power Inc 功能描述:50W 15V OUT 28V IN DC/DC - Bulk |
| NB50SI/24-C-D | 制造商:Martek Power Inc 功能描述:50W 24V OUT 28V IN DC/DC - Bulk |
| NB50SI/3.3-B | 制造商:Martek Power Inc 功能描述:50W 3.3V OUT 28V IN DC/DC - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。