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參數(shù)資料
| 型號(hào)： | NB4N840MMNG |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWITCH DUAL 32QFN |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 功能： | 交叉點(diǎn)開關(guān) |
| 電路： | 2 x 2:2 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 3.6 V |
| 電流 - 電源： | 130mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 托盤 |
NB4N840M
http://onsemi.com
3
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
ENB1
LVTTL
Channel B1 Output Enable. LVTTL low input powers down B1 output stage.
2
DB1
CML Input
Channel B1 Positive Signal Input
3
DB1
CML Input
Channel B1 Negative Signal Input
4
ENB0
LVTTL
Channel B0 Output Enable. LVTTL low input powers down B0 output stage.
5
SELB0
LVTTL
Channel B0 Output Select. See Table 1.
6
DB0
CML Input
Channel B0 Positive Signal Input
7
DB0
CML Input
Channel B0 Negative Signal Input
8
SELB1
LVTTL
Channel B1 Output Select. See Table 1.
9,24
GND
Supply Ground. All GND pins must be externally connected to power supply to guarantee
proper operation.
10, 13, 16,
17, 20, 23
VCC
Positive Supply. All VCC pins must be externally connected to power supply to guarantee
proper operation.
11
QB0
CML Output
Channel B0 Negative Output.
12
QB0
CML Output
Channel B0 Positive Output.
14
QB1
CML Output
Channel B1 Negative Output.
15
QB1
CML Output
Channel B1 Positive Output.
18
QA1
CML Output
Channel A1 Negative Output.
19
QA1
CML Output
Channel A1 Positive Output.
21
QA0
CML Output
Channel A0 Negative Output.
22
QA0
CML Output
Channel A0 Positive Output.
25
SELA1
LVTTL
Channel A1 Output Select, LVTTL Input. See Table 1.
26
DA0
CML Input
Channel A0 Positive Signal Input.
27
DA0
CML Input
Channel A0 Negative Signal Input.
28
SELA0
LVTTL
Channel A0 Output Select, LVTTL Input. See Table 1.
29
ENA0
LVTTL
Channel A0 Output Enable. LVTTL low input powers down A0 output stage.
30
DA1
CML Input
Channel A1 Positive Signal Input.
31
DA1
CML Input
Channel A1 Negative Signal Input.
32
ENA1
LVTTL
Channel A1 Output Enable. LVTTL low input powers down A1 output stage.
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing)
must be attached to a heatsinking conduit. The exposed pad must be soldered to the
circuit board GND for proper electrical and thermal operation.
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