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參數(shù)資料
| 型號(hào)： | NB4N7132DTG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SRL LINK REPLICATR HP 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 鏈路復(fù)制器，多路復(fù)用器 |
| PLL： | 無 |
| 主要目的： | 光纖通道，千兆位以太網(wǎng)，HDTV，SATA |
| 輸入： | LVPECL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
NB4N7132
http://onsemi.com
5
Figure 5. NB4N7132 Application Interface Example
NB4N7132
SerDes
TX+
TX
RX+
RX
O1+
O1
I1+
I1
I+
I
O+
O
O+
O
I+
I
I1+
I1
O1+
O1
RX+
RX
TX+
TX
0.01mF
R
RT
“R” is 150 W for both 100 W differential or 150 W differential traces.
“RT” matches the differential impedance of the link.
R
IN+/IN Input Functionality
The differential inputs are internally biased to
Y1.2 V. In
a typical application, the differential inputs are
capacitorcoupled and will swing symmetrically above and
below 1.2 V, preserving a 50% duty cycle to the outputs.
With this technique, the NB4N7132 will accept any
differential input allowing for LVPECL, CML, LVDS, and
HSTL input levels.
OUT+ / OUT Outputs
The OUT+ and OUT outputs of the NB4N7132 are
designed to drive differential transmission lines with
nominally 50
W or 75 W characteristic impedance. These
differential output buffers utilize positive emitter coupled
logic (PECL) architecture, but they do not require DC output
load resistors, and will operate properly with or without the
resistors.
OEx Output Enable
The NB4N7132 incorporates output enable pins, OE0 and
OE1, that work by powering down the output buffer and
associated driving circuitry. Using this approach results in
both differential outputs going HIGH, and a reduction in IDD
current of approx. 29 mA for each disabled output pair.
When OEx is LOW, outputs are disabled, OUTx+ and
OUTx are set HIGH.
Power Supply Bypass information
A clean power supply will optimize the performance of
the device. The NB4N7132 provides separate power supply
pins for the digital circuitry (VDD) and LVPECL outputs
(VDDPn). Placing a bypass capacitor of 0.01
mF to 0.1 mF
on each VDD pin will help ensure a noise free VDD power
supply. The purpose of this design technique is to try and
isolate the high switching noise of the digital outputs from
the relatively sensitive digital core logic.
Resource Reference of Application Notes
AND8002
Marking and Date Codes
AND8009
ECLinPS Plus Spice I/O Model Kit
ORDERING INFORMATION
Device
Package
Shipping
NB4N7132DTG
TSSOP28
(PbFree)
50 Units / Rail
NB4N7132DTR2G
TSSOP28
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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| NB4N7132DTR2G | 功能描述:通信集成電路 - 若干 2.5 GBPS SER LNK REP RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| NB4N840M | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination |
| NB4N840M_07 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination |
| NB4N840MMNEVB | 功能描述:BOARD EVAL BBG NB4N840MMN RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| NB4N840MMNG | 功能描述:模擬和數(shù)字交叉點(diǎn) IC ANA 2X2 CROSSPT SWCH CML RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
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