Table 5. AC CHARACTERISTICS VCC = 3" />
參數(shù)資料
型號(hào): NB4N316MDTG
廠商: ON Semiconductor
文件頁(yè)數(shù): 8/12頁(yè)
文件大小: 0K
描述: IC RCVR-CML DRVR/XLATOR 8-TSSOP
標(biāo)準(zhǔn)包裝: 100
邏輯類型: 差分接收器
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 管件
其它名稱: NB4N316MDTG-ND
NB4N316MDTGOS
NB4N316M
http://onsemi.com
5
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, VEE = 0 V; (Note 8)
Symbol
Characteristic
-40
°C
25
°C
85
°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOUTPP
Output Voltage Amplitude (RL = 50 W)
fin ≤ 1 GHz
(See Figure 12)
fin ≤ 1.5 GHz
fin ≤ 2.0 GHz
550
400
200
660
640
400
550
400
200
660
640
400
550
400
200
660
640
400
mV
VOUTPP
Output Voltage Amplitude (RL = 25 W)
fin ≤ 1 GHz
(See Figure 12)
fin ≤ 1.5 GHz
fin ≤ 2.0 GHz
280
200
370
360
300
280
200
370
360
400
280
200
370
360
400
mV
fDATA
Maximum Operating Data Rate
1.5
2.5
1.5
2.5
1.5
2.5
Gb/s
tPLH,
tPHL
Propagation Delay to Output Differential
@ 0.25 GHz
350
550
750
350
550
750
350
550
750
ps
tSKEW
Duty Cycle Skew (Note 9)
Device to Device Skew (Note 13)
2
20
100
2
20
100
2
20
100
ps
tJITTER
RMS Random Clock Jitter RL = 50 W and
RL = 25 W (Note 11)
fin = 750 MHz
fin = 1.5 GHz
fin = 2.0 GHz
Peak-to-Peak Data Dependent Jitter RL = 50 W
fDATA = 1.5 Gb/s
(Note 12)
fDATA = 2.5 Gb/s
Peak-to-Peak Data Dependent Jitter RL = 25 W
fDATA = 1.5 Gb/s
(Note 12)
fDATA = 2.5 Gb/s
1
15
20
5
10
3
55
85
35
1
15
20
5
10
3
55
85
35
1
15
20
5
10
3
55
85
35
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
200
mV
tr
tf
Output Rise/Fall Times @ 0.25 GHz
Q, Q
(20% - 80%)
150
300
150
300
150
300
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All output loaded with an external RL = 50 W and RL = 25 W to VTT.
Outputs must be connected through RL to VTT at power up. Input edge rates 150 ps (20% - 80%).
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ @ 0.25 GHz.
10. VINPP (MAX) cannot exceed VCC - VEE. Input voltage swing is a single-ended measurement operating in differential mode.
11. Additive RMS jitter with 50% duty cycle clock signal.
12. Additive peak-to-peak data dependent jitter with input NRZ data signal (PRBS 223-1).
13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) at Ambient Temperature (Typical)
0
100
200
300
400
500
600
700
800
0.75
1
1.25
1.5
1.75
2
RL = 50 W
RL = 25 W
INPUT CLOCK FREQUENCY (GHz)
OUTPUT
VOL
T
AGE
AMPLITUDE
(mV)
(VCC - VEE = 3.3 V VTT = 3.3 V @ 255C Vin = 100 mV)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.75
1
1.25
1.5
1.75
2
INPUT CLOCK FREQUENCY (GHz)
OUTPUT
VOL
T
AGE
AMPLITUDE
(mV)
(VCC - VEE = 3.0 V VTT = 1.71 V @255C Vin = 100 mV)
RL = 50 W
RL = 25 W
0.5
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