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參數(shù)資料
| 型號： | NB4L7210MNG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFF MUX 2:10 2GHZ 52-QFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVCMOS，LVDS，LVPECL，LVTTL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 2GHz |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 52-QFN（8x8） |
| 包裝： | 托盤 |
NB4L7210
http://onsemi.com
6
Programming Application Information for the SDI
To use the serial port, the SCLK signal samples the
information on the SDATA line and indexes the data into a
10 bit shift register (See Figure 3). The register shifts once
per rising edge of the SCLK input. The serial input SDATA
bits must each meet setup and hold timing to their respective
SCLK rising edge as specified in the AC Characteristics
section of this document. (See Figure 4)
The SDATA Least Significant Bit (LSB), D0, is indexed
in first and the Most Least Significant Bit (LSB), D9, is
indexed in last. A Pulse on the SLOAD pin after the SHIFT
register is fully indexed (10 clocks) will load and lock the
MUX select data values into the Latch register (See Figure
4). For each MUX (Output Q[0:9], a “0” bit value selects
CLK1 and a “1” bit value selects CLK 0 (see Figure 3, “C”).
As shown in Figure 4, the SLOAD pulse Low to HIGH
level transition transfers the data from the SHIFT register to
the LATCH register. The SLOAD Pulse HIGH to LOW level
transition will lock the new MUX select data values into the
LATCH register. An initial program load cycle is
recommended since the 10 bit register will powerup in a
random state.
SDATAOUT pin outputs the shift register LSB bit with
each SCLK rising edge for porting to the SCLK of the next
device in a cascade interconnect only. Cascade operation
will require a complete data register loading of all devices
to purge the shift registers of power up random state bits.
Figure 4. Serial Interface Timing Diagram
SCLK
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
C0
C1
C3
C4
C5
C6
C7
C8
C9
LSB
MSB
SLOAD
SDATA
PWmin
SDATA to SCLOCK
ts
th
ts
C2
SDATA to SLOAD
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