- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8681 > NB4L6254MNR4G (ON Semiconductor)IC CLK BUFFER MUX 1:6/1:3 32-QFN PDF資料下載
參數(shù)資料
| 型號： | NB4L6254MNR4G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFFER MUX 1:6/1:3 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 或 2 |
| 比率 - 輸入:輸出： | 1:6，1:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | LVCMOS，LVPECL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 3GHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 帶卷 (TR) |
NB4L6254
http://onsemi.com
8
Example Configurations
Figure 7. 2 x 2 Clock Switch
CLK0
CLK1
SEL0
SEL1
System A
System B
3
SEL0
SEL1
Switch Configuration
0
CLK0 Clocks System A and
0
1
CLK1 Clocks System A and
System B
1
0
CLK0 Clocks System A and CLK1
Clocks System B
1
CLK1 Clocks System B and CLK1
Clocks System A
Figure 8. 1:6 Clock Fanout Buffer
CLK0
CLK1
SEL0
SEL1
0
Figure 9. Loopback Device
SystemTx
CLK0
SEL0
SEL1
QBn
CLK1
Transmitter
QAn
SystemRx
Receiver
SEL0
SEL1
Switch Configuration
0
System Loopback
0
1
Line Loopback
1
0
Transmit/Receive Operation
1
System and Line Loopback
APPLICATIONS INFORMATION
Maintaining Lowest Device Skew
The NB4L6254 guarantees low outputoutput bank skew
at 50 ps and a parttopart skew of 250 ps. To ensure low
skew clock signals in the application, both outputs of any
differential output pair need to be terminated identically,
even if only one output is used. When fewer than all nine
output pairs are used, identical termination of all output pairs
within the output bank is recommended. If an entire output
bank is not used, it is recommended to leave all of these
outputs open and unterminated. This will reduce the device
power consumption while maintaining minimum output
skew.
Power Supply Bypassing
The NB4L6254 is a mixed analog/digital product. The
differential architecture of the NB4L6254 supports low
noise signal operation at high frequencies. In order to
maintain its superior signal quality all VCC pins should be
bypassed by highfrequency ceramic capacitors connected
to GND. If the spectral frequencies of the internally
generated switching noise on the supply pins cross the series
resonant port of an individual bypass capacitor, its overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the noise bandwidth.
Figure 10. VCC Power Supply Bypass
VCC
NB4L6254
33 100 nF
0.1 nF
VCC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V150A24H500BG | CONVERTER MOD DC/DC 24V 500W |
| NB4L6254FAR2G | IC CLK MUX SWITCH 1:6/1:3 32LQFP |
| VI-J74-MY | CONVERTER MOD DC/DC 48V 50W |
| VI-J73-MY | CONVERTER MOD DC/DC 24V 50W |
| MC100LVEP210FARG | IC CLOCK BUFFER 1:5 3GHZ 32-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB4L7210 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V/3.3V Differential 2x10 Crosspoint Clock Driver with SDI Programmable Output Selects |
| NB4L7210MNG | 功能描述:時鐘驅(qū)動器及分配 DIFF HSTL ECL PECL CLK RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| NB4L7210MNTXG | 制造商:ON Semiconductor 功能描述:DIFF HSTL ECL PECL CLK - Tape and Reel 制造商:Rochester Electronics LLC 功能描述: 制造商:ON Semiconductor 功能描述:REEL / DIFF HSTL ECL PECL CLK |
| NB4L858M | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V/3.3V, 3 GHz Dual Differential Clock/Data 2x2 Crosspoint Switch with CML Output and Internal Termination |
| NB4L858MFAG | 功能描述:模擬和數(shù)字交叉點(diǎn) IC DD CLK/DATA 2X2 CRPT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。