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參數(shù)資料
| 型號： | NB4L52MNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLIP FLOP DATA/CLK DFF 16-QFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 功能： | 復(fù)位 |
| 類型： | D 型 |
| 輸出類型： | 差分 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 1 |
| 延遲時間 - 傳輸： | 400ps |
| 觸發(fā)器類型： | 負(fù)邊沿 |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
NB4L52
http://onsemi.com
2
R
Figure 2. Pinout (Top View)
D
VTD
VCC
Q
CLK
Q
VTCLK
VEE
1
2
3
4
5
678
9
10
11
12
13
14
15
16
VTR
R
CLK
NB4L52
VTR
Exposed Pad (EP)
VTCLK
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTD
Internal 50 W Termination Pin. (See Table 4)
2
D
ECL, CML, LVCMOS,
LVDS, LVTTL Input
Noninverted Differential Input. (Note 1)
3
D
ECL, CML, LVCMOS,
LVDS, LVTTL Input
Inverted Differential Input. (Note 1)
4
VTD
Internal 50 W Termination Pin. (See Table 4)
5
VTCLK
Internal 50 W Termination Pin. (See Table 4)
6
CLK
ECL, CML, LVCMOS,
LVDS, LVTTL Input
Noninverted Differential Input. (Note 1)
7
CLK
ECL, CML, LVCMOS,
LVDS, LVTTL Input
Inverted Differential Input. (Note 1)
8
VTCLK
Internal 50 W Termination Pin. (See Table 4)
9
VEE
Negative Supply Voltage
10
Q
ECL Output
Inverted Differential Output. Typically terminated with 50 W resistor to VCC 2.0 V.
11
Q
ECL Output
Noninverted Differential Output. Typically terminated with 50 W resistor to VCC 2.0 V.
12
VCC
Positive Supply Voltage
13
VTR
Internal 50 W Termination Pin. (See Table 4)
14
R
LVECL, LVCMOS,
LVTTL Input
Noninverted Differential Reset Input. (Note 1)
15
R
LVECL, LVCMOS,
LVTTL Input
Inverted Differential Reset Input. (Note 1)
16
VTR
Internal 50 W Termination Pin. (See Table 4)
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die
for improved heat transfer out of package. The pad is not electrically connected to the die,
but is recommended to be electrically and thermally connected to VEE on the PC board.
1. In the differential configuration when the input termination pin (VTD, VTD, VTR, VTR, VTCLK, VTCLK) are connected to a common
termination voltage or left open, and if no signal is applied on D/D,CLK/CLK,R/R input then the device will be susceptible to selfoscillation.
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