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參數(shù)資料
| 型號： | NB4L16MMNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFFER DVR TRANSLA 16-QFN |
| 標準包裝： | 3,000 |
| 類型： | 緩沖器/驅動器，變換器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，HSTL，LVCMOS，LVDS，LVPECL，LVTTL |
| 輸出： | CML |
| 頻率 - 最大： | 3.5GHz |
| 電源電壓： | 2.375 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 16-QFN（3x3） |
| 包裝： | 帶卷 (TR) |
NB4L16M
http://onsemi.com
5
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOUTPP Output Voltage Amplitude (@VINPPmin)fin ≤ 3.5 GHz
fin ≤ 4.5 GHz
280
150
400
300
280
150
400
300
280
150
400
300
mV
fDATA
Maximum Operating Data Rate
3.5
5.0
3.5
5.0
3.5
5.0
Gb/s
tPLH,
tPHL
Propagation Delay to Output Differential @ 0.5 GHz
(Figure 6)
175
215
265
175
220
265
175
225
265
ps
tSKEW
Duty Cycle Skew (Note 9)
DevicetoDevice Skew (Note 13)
2.0
6.0
10
90
2.0
6.0
10
90
2.0
6.0
10
90
ps
tJITTER
RMS Random Clock Jitter (Note 11)
fin ≤ 4.5 GHz
PeaktoPeak Data Dependent Jitter
(Note 12)
fDATA = 2.5 Gb/s
fDATA = 3.5 Gb/s
fDATA = 5.0 Gb/s
0.2
1.5
2.0
9.0
0.7
10
12
25
0.2
1.5
2.0
9.0
0.7
10
12
25
0.2
1.5
2.0
9.0
0.7
10
12
25
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
75
VCC
VEE
75
VCC
VEE
75
VCC
VEE
mV
tr
tf
Output Rise/Fall Times @ 0.5 GHz
(Figure 5)
(20% 80%)
60
90
60
90
60
90
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing VINPP(MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+ @ 0.5 GHz.
10.VINPP(MAX) cannot exceed VCC VEE. Input voltage swing is a singleended measurement operating in differential mode. See Figure 11.
11. Additive RMS jitter with 50% duty cycle input clock signal.
12.Additive peaktopeak data dependent jitter with NRZ input data signal, PRBS 2231 and K28.7 pattern. See Figures 7, 8, 9, 10, 11 and 12.
13.Devicetodevice skew is measured between outputs under identical transition @ 0.5 GHz.
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