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參數(shù)資料
| 型號(hào)： | NB3N3002DTG |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN XTAL-HCSL 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 類型： | 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | HCSL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
NB3N3002
http://onsemi.com
5
Table 7. AC ELECTRICAL CHARACTERISTICS PCI EXPRESS JITTER SPECIFICATIONS,
VDD = 3.3 V ± 5%, TA = 40°C to 85°C
Symbol
Characteristic
Test Conditions
Min
Typ
Max
PCIe Inductry
Spec
Unit
Phase Jitter
PP
(Notes 11
and 14)
TJ
PCIe Gen1
= 100 MHz, 25 MHz Crystal
Input
Evaluation Band: 0 Hz Nyquist
(clock frequency/2)
6
21
86
ps
Phase Jitter
RMS
(Notes 11
and 14)
tREFCLK_HF_RMS
(PCIe Gen 2)
= 100 MHz, 25 MHz Crystal
Input
High Band: 1.5 MHz Nyquist
(clock frequency/2)
0.6
3
3.1
ps
Phase Jitter
RMS
(Notes 11
and 14)
tREFCLK_LF_RMS
(PCIe Gen 2)
= 100 MHz, 25 MHz Crystal
Input
Low Band: 10 kHz 1.5 MHz
0.08
0.3
3
ps
Phase Jitter
RMS
(Notes 13
and 14)
tREFCLK_RMS
(PCIe Gen 3)
= 100 MHz, 25 MHz Crystal
Input
Evaluation Band: 0 Hz Nyquist
(clock frequency/2)
0.23
0.7
0.8
ps
10.Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
11. PeaktoPeak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86 ps
peaktopeak for a sample size of 106 clock periods.
12.RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the
worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1 ps RMS for tREFCLK_HF_RMS (High Band)
and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
13.RMS jitter after applying system transfer function for the common clock architecture.
14.This parameter is guaranteed by characterization. Not tested in production
Figure 3. Typical Termination for Output Driver and Device Evaluation
Zo = 50 W
RL = 49.9 W
RL =
49.9 W
RL = 33.2 W
HCSL
Driver
HCSL
Receiver
RREF = 475 W
IREF
Figure 4. HCSL Output Parameter Characteristics
tR
tF
525 mV
175 mV
525 mV
175 mV
340 ps
700 mV
0 mV
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