參數(shù)資料
型號: NB3N206SDR2G
廠商: ON Semiconductor
文件頁數(shù): 8/19頁
文件大?。?/td> 0K
描述: IC CLK DVR RECEIVER M-LVDS 8SOIC
標準包裝: 2,500
類型: 緩沖器/驅(qū)動器
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
輸入: LVCMOS,LVDS
輸出: LVCMOS,LVDS
頻率 - 最大: 200MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 帶卷 (TR)
NB3N201S, NB3N206S
http://onsemi.com
16
Figure 17. MLVDS Receiver Output: VCC (CHANNEL 1), R Pin (CHANNEL 2)
Simplex Theory Configurations: Data flow is
unidirectional and PointtoPoint from one Driver to one
Receiver. NB3N201SDG and NB3N206SDG devices
provide a high signal current allowing long drive runs and
high noise immunity. Single terminated interconnects yield
high amplitude levels. Parallel terminated interconnects
yield typical MLVDS amplitude levels and minimizes
reflections. See Figures 18 and 19. A NB3N201SDG and
NB3N206SDG can be used as the driver or as a receiver.
Figure 18.
PointtoPoint Simplex Single
Termination
Figure 19. ParallelTerminated Simplex
Simplex Multidrop Theory Configurations: Data flow is
unidirectional from one Driver with one or more Receivers
Multiple boards required. Single terminated interconnects
yield high amplitude levels. Parallel terminated
interconnects yield typical MLVDS amplitude levels and
minimizes reflections. On the Evaluation Test Board,
Headers P1, P2, and P3 may be used as need to interconnect
transceivers to a each other or a bus. See Figures 20 and 21.
A NB3N201SDG and NB3N206SDG can be used as the
driver or as a receiver.
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