參數(shù)資料
型號(hào): NB3N121KMNG
廠商: ON Semiconductor
文件頁數(shù): 5/11頁
文件大小: 0K
描述: IC FANOUT BUFFER 1:21 52QFN
標(biāo)準(zhǔn)包裝: 260
類型: 扇出緩沖器(分配),數(shù)據(jù)
電路數(shù): 1
比率 - 輸入:輸出: 1:21
差分 - 輸入:輸出: 是/是
輸入: HCSL, LVCMOS, LVDS, LVPECL, LVTTL
輸出: HCSL,LVDS
頻率 - 最大: 400MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 52-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 52-QFN(8x8)
包裝: 托盤
NB3N121K
http://onsemi.com
3
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
IREF
Output
Use the IREF pin to set the output drive. Connect a 475 W RREF resist-
or from the IREF pin to GND to produce 2.63 mA of IREF current. A
current mirror multiplies IREF by a factor of 5.4 to force 14.2 mA through
a 50 W output load. See Figures 6 and 12. Minimize capacitance.
2
GND
Supply Ground. GND pin must be externally connected to power supply
to guarantee proper operation.
3, 6
VTCLK,
VTCLK
Internal 50 W Termination Resistor connection Pins. In the differential
configuration when the input termination pins are connected to the com-
mon termination voltage, and if no signal is applied then the device may
be susceptible to selfoscillation.
4
CLK
LVPECL,
HCSL,
LVCMOS or
LVTTL Input
Clock (TRUE) Input
5
CLK
LVPECL,
HCSL,
LVCMOS or
LVTTL Input
Clock (INVERT) Input
7, 26, 39, 52
VCC
Positive Supply pins. VCC pins must be externally connected to a power
supply to guarantee proper operation.
8, 10, 12, 14, 16, 18, 20, 22,
24, 27, 29, 31, 33, 35, 37,
40,42, 44, 46, 48, 50
Q[200]
HCSL or LVDS
(Note 1) Output
Output (INVERT) (Note 1)
9, 11, 13, 15, 17, 19, 21, 23,
25, 28, 30, 32, 34, 36, 38,
41, 43, 45, 47, 49, 51
Q[200]
HCSL or LVDS
(Note 1) Output
Output (TRUE) (Note 1)
Exposed Pad
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see
case drawing) must be attached to a sufficient heatsinking conduit for
proper thermal operation. The pad is electrically connected ot GND and
must be connected to GND on the PC board.
1. Outputs can also interface to LVDS receiver when terminated per Figure 11.
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