
NB3N111K
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6
Figure 4. SingleEnded Interconnect
Vth Reference Voltage
CLK
Vth
CLK
Vth
Figure 5. Vth Diagram
VCC
VEE
VCMRmin
VCMRmax
VCMR
IN
VIHDmax
VILDmax
VID = VIHD VILD
VIHDtyp
VILDtyp
VIHDmin
VILDmin
Figure 6. Typical Termination Configuration for Output Driver and Device Evaluation
A. Connect 475 W resistor RREF from IREF pin to GND.
B. RS1, RS2: 0 W for Test and Evaluation. Select to Minimizing Ringing.
C. CL1, CL2: Receiver Input Simulation (for test only not added to application circuit)
Load capacitance only.
D. DL1, DL2 Termination and Load Resistors Located at Receiver Inputs.
CL1C
2 pF
CL2C
2 pF
Z0 = 50 W
Receiver
RS1B
RS2B
HCSL
Driver
RREFA
RL1D
50 W
RL2D
50 W
Qx
IREF
50 W*
VTCLK = VTCLK = VCC 2.0 V
LVPECL
Driver
Z0 = 50 W
VCC = 3.3 V / 2.5 V
VCC = 3.3 V
GND
50 W*
VTCLK
CLK
Figure 7. LVPECL Interface
*RTIN, Internal Input Termination Resistor
50 W*
VTCLK = VTCLK
LVDS
Driver
Z0 = 50 W
VCC = 3.3 V / 2.5 V / 1.8 V
VCC = 3.3 V
GND
50 W*
VTCLK
Figure 8. LVDS Interface
*RTIN, Internal Input Termination Resistor
NB3N111K
CLK