參數(shù)資料
型號(hào): NB3N108KMNG
廠商: ON Semiconductor
文件頁(yè)數(shù): 2/9頁(yè)
文件大?。?/td> 0K
描述: IC FANOUT BUFFER 1:8 HCSL 32QFN
標(biāo)準(zhǔn)包裝: 74
類(lèi)型: 扇出緩沖器(分配),數(shù)據(jù)
電路數(shù): 1
比率 - 輸入:輸出: 1:8
差分 - 輸入:輸出: 是/是
輸入: HCSL, LVCMOS, LVDS, LVPECL, LVTTL
輸出: HCSL,LVDS
頻率 - 最大: 400MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-QFN(5x5)
包裝: 管件
NB3N108K
http://onsemi.com
2
Figure 2. Pinout Configuration (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
1314
1516
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NB3N108K
IREF
VTCLK
CLK
VTCLK
GND
VCC
Q7
Q6
VCC
NC
VCC
Q3
Q4
VCC
Q0
Q1
VCC
Q5
Q2
Exposed Pad (EP)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
IREF
Use the IREF pin to set the output drive. Connect a 475 W RREF
resistor from the IREF pin to GND to produce 2.6 mA of IREF current. A
current mirror multiplies IREF by a factor of 5.4x to force 14 mA through
a 50 W output load. See Figures 6 and 12.
2, 5
VTCLK,
VTCLK
Internal 50 W Termination Resistor connection Pins. In the differential
configuration when the input termination pins are connected to the com-
mon termination voltage, and if no signal is applied then the device may
be susceptible to selfoscillation.
3
CLK
LVPECL HCSL, LVDS
Input
Clock (TRUE) Input
4
CLK
LVPECL HCSL, LVDS
Input
Clock (INVERT) Input
12, 14, 18, 20,
22, 26, 28, 30
Q[70]b
HCSL or LVDS (Note 1)
Output
Output (INVERT) (Note 1)
13, 15, 19, 21,
23, 27, 29, 31
Q[70]
HCSL or LVDS (Note 1)
Output
Output (TRUE) (Note 1)
6, 7, 10, 11
NC
No Connect
8
GND
Supply Ground. GND pin must be externally connected to power supply
to guarantee proper operation.
9, 16, 17, 24, 25,
32
VCC
Positive Voltage Supply pin. VCC pins must be externally connected to
a power supply to guarantee proper operation.
Exposed Pad
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see
case drawing) must be attached to a sufficient heatsinking conduit for
proper thermal operation and electrically connected to the circuit board
ground (GND).
1. Outputs can also interface to LVDS receiver when terminated per Figure 11.
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