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參數(shù)資料
型號: NB100LVEP17MNR2
廠商: ON Semiconductor
文件頁數(shù): 3/10頁
文件大?。?/td> 0K
描述: IC DRVR ECL QUAD 2.5V/3.3V 24QFN
產(chǎn)品變化通告: Product Obsolescence 11/Feb/2009
標準包裝: 1
系列: 100LVEP
邏輯類型: 差分接收器/驅(qū)動器
電源電壓: 2.375 V ~ 3.8 V
位數(shù): 4
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 剪切帶 (CT)
其它名稱: NB100LVEP17MNOSCT
NB100LVEP17
http://onsemi.com
2
D1
D2
Q0
Q1
VEE
D0
Q0
D2
D0
D3
VCC
Figure 1. Logic Diagram
Q2
Q3
Q2
VBB
R1
R2
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default
State
Description
TSSOP
QFN
1,20
13,18,21,
22,23
VCC
Positive Supply Voltage. All VCC Pins Must be Externally Connected
to Power Supply to Guarantee Proper Operation.
11
10
VEE
Negative Supply Voltage. All VEE Pins Must be Externally Con-
nected to Power Supply to Guarantee Proper Operation.
10
9
VBB
ECL Reference Voltage Output.
2,4,6,8
1,3,5,7
D[0:3]
ECL Input
Low
Noninverted Differential Inputs [0:3]. Internal 75 kW to VEE.
3,5,7,9
2,4,6,8
D[0:3]
ECL Input
High
Inverted Differential Inputs [0:3]. Internal 75 kW to VEE and 37 kW to
VCC.
19,17,15,13
12,15,17,2
0
Q[0:3]
ECL Output
Noninverted Differential Outputs [0:3]. Typically Terminated with
50 W to VTT = VCC 2 V.
18,16,14,12
11,14,16,1
9
Q[0:3]
ECL Output
Inverted Differential Outputs [0:3]. Typically Terminated with 50 W to
VTT = VCC 2 V.
N/A
24
NC
No Connect. The NC Pin is Electrically Connected to the Die and
“MUST BE” Left Open.
N/A
EP
Exposed Pad. (Note 1)
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally conductive expose pad
on the package bottom (see case drawing) must be attached to a heatsinking conduit.
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