Table 8. AC CHARACTERISTICS VCC =" />
參數(shù)資料
型號: NB100EP223FA
廠商: ON Semiconductor
文件頁數(shù): 6/10頁
文件大?。?/td> 0K
描述: IC CLOCK BUFFER MUX 2:22 64-LQFP
產(chǎn)品變化通告: Product Obsolescence 01/Jul/2005
標(biāo)準(zhǔn)包裝: 160
系列: 100EP
類型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:22
差分 - 輸入:輸出: 是/是
輸入: HSTL,LVDS,LVPECL
輸出: HSTL
頻率 - 最大: 500MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
其它名稱: NB100EP223FAOS
NB100EP223
http://onsemi.com
5
Table 8. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V; GND = 0 V (Note 4)
Symbol
Characteristic
0°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOpp
Differential Output Voltage
(Figure 3)
fout < 500 MHz
600
750
600
750
600
700
mV
tPLH
tPHL
Propagation Delay (Differential)
LVPECL_CLK to Q
HSTL_CLK to Q
700
800
900
1000
1100
750
850
900
950
1100
1200
800
850
1000
1050
1300
1350
ps
tskew
WithinDevice Skew (Note 5)
DevicetoDevice Skew (Note 6)
25
100
50
250
30
200
65
450
50
250
115
450
ps
tJITTER
Random Clock Jitter (Figure 3) (RMS)
0.5
2
0.5
2
0.5
2
ps
VPP
Input Swing (Differential Mode)
(Note 8) (Figure 4)
LVPECL, HSTL
150
800
1200
150
800
1200
150
800
1200
mV
tS
OE Set Up Time (Note 7)
1.0
ns
tH
OE Hold Time
0.5
ns
tr/tf
Output Rise/Fall Time (20%80%)
300
450
700
275
450
700
350
500
750
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 W to ground
(See Figure 6).
5. Skew is measured between outputs under identical transitions and conditions on any one device.
6. DevicetoDevice skew for identical transitions at identical VCC levels.
7. OE Set Up Time is defined with respect to the rising edge of the clock. OE HightoLow transition ensures outputs remain disabled during
the next clock cycle. OE LowtoHigh transition enables normal operation of the next input clock (See Figure 7).
8. VPP is the differential input voltage swing required to maintain AC characteristics including tPD and devicetodevice skew.
Figure 3. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER)
FREQUENCY (GHz)
0.5
0.6
0.7
0.8
0.9
1.0
800
900
700
600
500
400
300
200
OUTPUT
AMPLITUDE
(mV)
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
10
RMS
JITTER
(ps)
Q AMP (mV)
RMS JITTER (ps)
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