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參數(shù)資料
| 型號： | NAND512W3B3AN1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| 封裝： | 12 X 20 MM, PLASTIC, TSOP-48 |
| 文件頁數(shù)： | 14/59頁 |
| 文件大?。?/td> | 998K |
| 代理商： | NAND512W3B3AN1 |
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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
Cache Read
The Cache Read operation is used to improve the
read throughput by reading data using the Cache
Register. As soon as the user starts to read one
page, the device automatically loads the next page
into the Cache Register.
An Cache Read operation consists of three steps
(see Table 10.):
1.
One bus cycle is required to setup the Cache
Read command (the same as the standard
Read command)
2.
bus cycles are then required to input the Start
Address
3.
One bus cycle is required to issue the Cache
Read confirm command to start the P/E/R
Controller.
The Start Address must be at the beginning of a
page (Column Address = 00h, see Table 8. and
Table 9.). This allows the data to be output unin-
The Ready/Busy signal can be used to monitor the
start of the operation. During the latency period the
Ready/Busy signal goes Low, after this the Ready/
Busy signal goes High, even if the device is inter-
nally downloading page n+1.
Once the Cache Read operation has started, the
Status Register can be read using the Read Status
Register command.
During the operation, SR5 can be read, to find out
whether the internal reading is ongoing (SR5 =
‘0’), or has completed (SR5 = ‘1’), while SR6 indi-
cates whether the Cache Register is ready to
download new data.
To exit the Cache Read operation an Exit Cache
Read command must be issued (see Table 10.).
If the Exit Cache Read command is issued while
the device is internally reading page n+1, page n
will still be output, but not page n+1.
Figure 11. Cache Read Operation
I/O
RB
Address
Inputs
ai08661
00h
Read
Setup
Code
31h
Cache
Read
Confirm
Code
Busy
tBLBH1
(Read Busy time)
1st page
Data Output
2nd page
3rd page
last page
34h
Exit
Cache
Read
Code
Block N
相關PDF資料 |
PDF描述 |
|---|---|
| NAND512W3B3BN1F | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND04GR4B3AN1 | 256M X 16 FLASH 1.8V PROM, 35 ns, PDSO48 |
| NAND02GW3B3BZB1F | 256M X 8 FLASH 3V PROM, 35 ns, PBGA63 |
| NAND02GW3B3BN1F | 256M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND02GW3B3CN6 | 256M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| NAND512W4A0AN6E | 功能描述:閃存 NAND & S.MEDIA FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| NAND512W4A0AZA6E | 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL 3V/3.3V 512MBIT 32MX16 12US 63VFBGA - Trays |
| NAND64GAH0HZA5F | 制造商:Micron Technology Inc 功能描述:NAND EMMC - Tape and Reel |
| NAND64GW3FGAZN6F | 制造商:Micron Technology Inc 功能描述:FULL CUSTOM MCP - Tape and Reel |
| NAND98R3M0CZBB5E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
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