參數(shù)資料
型號(hào)： NAND01GR4N5
廠商： Electronic Theatre Controls, Inc.
英文描述： 1 Gbit (x8/x16) 2112 Byte Page NAND Flash Memory and 512 Mbit (x16) LPSDRAM, 1.8V, Multi-Chip Package
中文描述： 1千兆位（x8/x16）2112字節(jié)頁(yè)NAND閃存和512兆位（x16）的同一封裝內(nèi)整合，1.8，多芯片封裝
文件頁(yè)數(shù)： 1/23頁(yè)
文件大?。?/td> 238K
代理商： NAND01GR4N5
PRELIMINARY DATA
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
January 2006
Rev1.0
1/23
2
NAND01G-N
1 Gbit (x8/x16) 2112 Byte Page NAND Flash Memory and
512 Mbit (x16) LPSDRAM, 1.8V, Multi-Chip Package
Features summary
■
Multi-chip Package
– NAND Flash Memory
– 512 Mbit or 1 Gbit (x8/x16) Large Page
Size NAND Flash Memory
– 512 Mbit (x16) SDR or DDR LPSDRAM
■
Temperature range
– -30 up to 85 °C
■
Supply voltage
– NAND Flash : V
DDF
= 1.7V to 1.95V
– LPSDRAM: V
DDD
= V
DDQD
= 1.7V to 1.9V
■
Electronic Signature
■
ECOPACK
packages
Flash Memory
■
Nand Interface
– x8 or x16 bus width
– Multiplexed address/data
■
Page size
– x8 device: (2048 + 64 spare) Bytes
– x16 device: (1024 + 32 spare) Words
■
Block size
– x8 device: (128K + 4K spare) Bytes
– x16 device: (64K + 2K spare) Words
■
Page Read/Program
– Random access: 25μs (max)
– Sequential access: 50ns (min)
– Page program time: 300μs (typ)
■
Copy Back Program mode
– Fast page copy without external buffering
■
Fast Block Erase
– Block Erase time: 2ms (typ)
■
Chip Enable ‘don’t care’
– for simple interfacing with microcontrollers
■
Status Register
SDR/DDR LPSDRAM
■
Interface: x16 bus width
■
Programmable Partial Array Self Refresh
■
Auto Temperature Compensated Self Refresh
■
Deep Power Down mode
■
1.8V LVCMOS interface
■
Quad internal Banks controlled by BA0 and
BA1
■
Wrap sequence: Sequential/Interleaved
■
Automatic and Controlled Precharge
■
Auto Refresh and Self Refresh
■
8,192 Refresh Cycles/64ms
■
Burst Termination by Burst Stop command and
Precharge Command
FBGA
TFBGA107 10.5 x 13 x 1.2mm
TFBGA149 10 x 13.5 x 1.2mm
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