參數(shù)資料
型號： N80930HF
廠商： INTEL CORP
元件分類： 總線控制器
英文描述： Universal Serial Bus Microcontroller(通用串行總線微控制器)
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 1/38頁
文件大小： 304K
代理商： N80930HF
ADVANCE INFORMATION
COPYRIGHT INTEL CORPORATION, 1997
May 1997
Order Number: 272928-003
8x930Hx
UNIVERSAL SERIAL BUS HUB
PERIPHERAL CONTROLLER
I
USB Hub with One Upstream, One
Internal Downstream, and Three
External Downstream Ports on HD/HE
Parts or Four on HF/HG Parts
— Complete Universal Serial Bus Speci-
fication 1.0 Compatibility
— Serves as both USB Hub and USB
Embedded Function (Internal Port)
I
USB Hub
— Connectivity Management
— Downstream Device
Connect/Disconnect Detection
— Power Management, Including
Suspend and Resume
— Bus Fault Detection and Recovery
— Full and Low Speed Downstream
Device Support
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Output Pin for Port Power Switching
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Input Pin for Overcurrent Detection
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USB Embedded Function
— Supports Isochronous and
Non-isochronous Data
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On-chip USB Transceivers
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Serial Bus Interface Engine (SIE)
— Packet Decoding/Generation
— CRC Generation and Checking
— NRZI Encoding/Decoding and
Bit-stuffing
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Hub FIFO Data Buffers
— One Pair of 16-byte Transmit and
Receive FIFOs
— One 1-byte Transmit Register
The 8x930Hx USB hub peripheral controller is based on the MCS
251 microcontroller. It consists of standard
8XC251Sx peripherals plus a USB module. The USB module provides both USB hub and USB embedded
function capabilities. The 8x930Hxsupports USB hub functionality, embedded function, suspend/resume
modes, isochronous/non-isochronous transfers, and it is fully USB rev 1.0 specification compliant. The USB
module contains one internal and three (or four) external downstream ports and integrates the USB trans-
ceivers, serial bus interface engine (SIE), hub interface unit (HIU), function interface unit (FIU), and
transmit/receive FIFOs. The 8x930Hx uses the standard instruction set of the MCS 251 architecture, which is
binary code compatible with the MCS
51 architecture.
I
Embedded Function FIFO Data Buffers
— Three Pairs of 16-byte Transmit and
Receive FIFOs
— One Pair of Configurable Transmit
and Receive FIFOs (1 Kbyte total)
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Automatic Transmit/Receive FIFO
Management
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Three USB Interrupt Vectors
— Endpoint Transmit/Receive Done
— Start of Frame/Hub Endpoint Done
— Global Suspend/Resume
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Low Clock Mode
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User-selectable Configurations
— External Wait State
— External Address Range
— Page Mode
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Real-time Wait Function
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256-Kbyte External Code/Data Memory
Space
I
On-chip ROM Options
— 0, 8, or 16 Kbytes
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1024 bytes On-chip Data RAM
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Four Input/Output Ports
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Standard MCS
51 UART
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Power-saving Idle and Powerdown
Modes
I
Register-based MCS
251 Architecture
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Code-compatible with MCS 51 and
MCS 251 Microcontrollers
I
12-MHz Crystal Operation
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