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參數(shù)資料
| 型號： | N74F574N,602 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 11/14頁 |
| 文件大小： | 0K |
| 描述： | IC TRANSP LATCH OCTAL 3ST 20DIP |
| 產(chǎn)品培訓(xùn)模塊： | Logic Packages |
| 標(biāo)準(zhǔn)包裝： | 720 |
| 系列： | 74F |
| 功能： | 標(biāo)準(zhǔn) |
| 類型： | D 型總線 |
| 輸出類型： | 三態(tài)非反相 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 8 |
| 頻率 - 時鐘： | 100MHz |
| 延遲時間 - 傳輸： | 3.2ns |
| 觸發(fā)器類型： | 正邊沿 |
| 輸出電流高，低： | 3mA，24mA |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
Philips Semiconductors
Product specification
74F573/74F574
Latch/flip-flop
1989 Oct 16
6
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
NO TAG
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONSNO TAG
MIN
TYP
NO TAG
MAX
UNIT
VO
High level output voltage
VCC = MIN, VIL = MAX,
±10%VCC
2.4
V
VOH
High-level output voltage
VCC
MIN, VIL
MAX,
VIH = MIN, IOH = MAX
±5%VCC
2.7
3.4
V
VO
Low level output voltage
VCC = MIN, VIL = MAX,
±10%VCC
0.35
0.50
V
VOL
Low-level output voltage
VCC
MIN, VIL
MAX,
VIH = MIN, IOL = MAX
±5%VCC
0.35
0.50
V
VIK
Input clamp voltage
VCC = MIN, II = IIK
–0.73
–1.2
V
II
Input current at
maximum input voltage
VCC = MAX, VI = 7.0V
100
A
IIH
High-level input current
VCC = MAX, VI = 2.7V
20
A
IIL
Low-level input current
VCC = MAX, VI = 0.5V
–0.6
mA
IOZH
Off-state output current,
High-level voltage applied
VCC = MAX, VO = 2.7V
50
A
IOZL
Off-state output current,
Low-level voltage applied
VCC = MAX, VO = 0.5V
–50
A
IOS
Short-circuit output currentNO TAG
VCC = MAX
–60
–150
mA
ICCH
30
40
mA
ICCL
74F573
VCC = MAX
35
50
mA
ICC
Supply
current
ICCZ
40
60
mA
ICC
current
(total)
ICCH
45
65
mA
()
ICCL
74F574
VCC = MAX
50
70
mA
ICCZ
55
85
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
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