參數(shù)資料
型號: N74F260N,602
廠商: NXP Semiconductors
文件頁數(shù): 8/8頁
文件大?。?/td> 0K
描述: IC GATE NOR 5INPUT 14DIP
標準包裝: 25
系列: 74F
邏輯類型: 或非門
電路數(shù): 2
輸入數(shù): 5
電源電壓: 4.5 V ~ 5.5 V
輸出電流高,低: 1mA,20mA
邏輯電平 - 低: 0.8V
邏輯電平 - 高: 2V
額定電壓和最大 CL 時的最大傳播延遲: 5.5ns @ 5V,50pF
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
供應(yīng)商設(shè)備封裝: 14-DIP
封裝/外殼: 14-DIP(0.300",7.62mm)
包裝: 管件
其它名稱: 933769280602
N74F260N
N74F260N-ND
2000 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7WZ132 Rev. 1.11.0
8
Physical Dimensions
Figure 4. 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specications do not expand the terms of Fairchild’s worldwide terms and conditions,
specically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
0.30 TYP
SEATING PLANE
0.10-0.18
0.13
A B
C
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
D. DIMENSIONS AND TOLERANCES PER ANSI Y14.5M, 1982.
AND TIE BAR EXTRUSIONS.
MAB08AREVC
0.50TYP
B. DIMENSIONS ARE IN MILLIMETERS.
A. CONFORMS TO JEDEC REGISTRATION MO-187
-C-
0.17-0.27
0.10
0.00
DETAIL A
0°-8°
0.4 TYP
-B-
0.70±0.10
ALL LEAD TIPS
0.2 C B A
3.1±.1
0.15
PIN #1 IDENT.
0.90 MAX
ALL LEAD TIPS
0.1 C
1.55
8
1
4
2.3±0.1
5
-A-
0.70
2.70
3.40
1.00
0.5 TYP
DETAIL A
1.80
GAGE PLANE
0.12
NC7WZ132
Tin
yLogic
UHS
Dual
2-Input
NAND
Gate
with
Sc
hmitt
T
rig
g
er
Inputs
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