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參數(shù)資料
| 型號： | MX98905BFC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| 中文描述： | 該MX98905是專為易于實現(xiàn)的多址/光盤局域網(wǎng)， |
| 文件頁數(shù)： | 52/86頁 |
| 文件大?。?/td> | 352K |
| 代理商： | MX98905BFC |
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52
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
6. INTERRUPT STATUS REGISTER (ISR) 07H (READ/WRITE)
(Continued)
SYMBOL
BIT
DESCRIPTION
CNT
D5
COUNTER OVERFLOW
: Set when MSB of one or more of the Network Tally Counters
has been set.
RDC
D6
REMOTE DMA COMPLETE
: Set when Remote DMA operation has been completed.
RST
D7
RESET STATUS
: Set when ENC enters reset state and cleared when a start command
is issued to the CR. This bit is also set when a Receive Buffer Ring overflow occurs and
is cleared when one or more packets has been removed from the ring. Writing to this bit
has no effect.
Note: This bit does not generate any interrupt; it is merely a status indicator.
7. INTERRRUPT MASK REGISTER (IMR) 0FH
(WRITE)
The Interrupt Mask Register is used to mask interrupts.
Each interrupt mask bit corresponds to a bit in the
Interrupt Status Register (ISR). If an interrupt mask bit
is set, an interrupt will be issued whenever the corre-
sponding bit in the ISR is set. If any bit in the IMR is set
low, an interrupt will not occur when the bit in the ISR
is set. The IMR powers up all zeros.
PRXE
PTXE
RXEE
TXEE
OVWE
CNTE
RDCE
0
1
2
3
4
5
6
7
x
Bits
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相關代理商/技術參數(shù) |
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|---|---|
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