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參數(shù)資料
| 型號(hào)： | MX98748 |
| 英文描述： | Highly Intergated 10/100M Dual Speed Hub With Extra 4 Port Switch Built-In |
| 中文描述： | 高Intergated個(gè)10/100M額外雙速集線器4端口交換機(jī)內(nèi)置 |
| 文件頁數(shù)： | 7/36頁 |
| 文件大小： | 166K |
| 代理商： | MX98748 |
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7
MX98745
P/N:PM0427
REV. 1.4, JUL. 8, 1998
D. Management, 2 pins
PAD #
38
Name
MDC
I/O
I,
TTL
I/O,
TTL
Description
Management Data Clock. The timing reference for MDIO.
The minumum high and low times are 200 ns each.
Management Data Input/Output. A bi-directional signal.
The selection of input/output direction is based on IEEE802.3u management
functions (Section 22.2.4).
39
MDIO
E. Test/Miscellaneous, 5 pins
PAD #
33
Name
TEST
I/O
I
Description
Test. Industrial test pin. Set to 0 for normal operation.
When programmed to logic 1, XRC II is in test mode.
Test Select. Used by industrial test. Internal Pulldown.
Set to 0 for normal operation.
Collision LED. Active low. When there is collision within the XRC II, XCOLED
will be on for 80ms and off for 20ms.
Scrambler Control. Active High. When this pin is set to 0. All TX port will be
set to descramble mode, i.e. contents of register #17 will be disabled. When
this pin is set to 1. Each port's scrambler/descrambler is controller by corre
sponding bit in register #17. Internally pullup.
Reset. Active Low. Will be filtered by LSCLK within the MX98745.
32
TSEL
I
34
XCOLED
O,
LED
I,
TTL
35
SCRCTRL
36
RESETL
I,
Sche
I,
TTL
31
IBMON
Internal Bus Monitor. In house debugging usage. Internally pull down.
Table 5-1 Pin Description for XRC II (Continued)
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