參數(shù)資料
型號(hào)： MX98725
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE CHIP FAST ETHERNET NIC CONTROLLER
中文描述： 單晶片快速以太網(wǎng)卡控制器
文件頁(yè)數(shù)： 6/33頁(yè)
文件大小： 177K
代理商： MX98725
6
P/N:PM0488
REV. 1.7, SEP. 15, 1998
MX98725
5. PROGRAMMING INTERFACE
5.1 PCI CONFIGURATION REGISTERS :
5.1.1 PCI ID REGISTER ( PFID ) ( Offset 03h-00h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Device ID (bit 31:16)
Vendor ID (bit 15:0)
This register can be loaded from external serial EEPROM or use a MXIC preset value of "0D9" and "0531" for vendor
ID and device ID respectively. Word location 3Eh and 3Dh in serial EEPROM are used to configure customer's
vendor ID and device ID respectively. If location 3Eh contains"FFFF" value then MXIC's vendor ID and device ID will
be set in this register, otherwise both 3Eh and 3Dh will be loaded into this register from serial EEPROM.
5.1.2 PCI COMMAND AND STATUS REGISTER ( PFCS ) ( Offset 07h-04h )
The bit content will be reset to 0 when a 1 is written to the corresponding bit location.
bit 0 : IO Space Access, set to 1 enable IO access
bit 1 : Memory Space Access, set to 1 to enable memory access
bit 2 : Master Operation, set to 1 to support bus master mode
bit 5-3 : not used
bit 6 : Parity Error Response, set to 1 to enable assertion of CSR<13> bit if parity error detected.
bit 7 : not used
bit 8 : System Error Enable, set to 1 to enable SERR# when parity error is detected on address lines and CBE[3:0].
bit 20 : New capability. Set to support PCI power management.
bit 22-bit19 : not used
bit 23 : Fast Back-to back, always set to accept fast back-to-back transactions that are not sent to the same bus
device.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Detect Party Error
Signal System Error
Data Parity Report
Fast Back-to-back
New Capability
System Error Enable
Parity Error Response
Master Operation
Memory Space Access
IO Space Access
Receive Master Abort
Receive Target Abort
Deceive Select Timing
相關(guān)PDF資料
PDF描述
MX98905B The MX98905 is designed for easy implementation of CSMA/CD local area networks,
MX98905B IEEE 802.3, 10BASE5, 10BASE2 Controller and Integrated Bus Interface(IEEE 802.3, 10BASE5, 10BASE2控制器和集成總線接口)
MX98905BFC The MX98905 is designed for easy implementation of CSMA/CD local area networks,
MXA2312A Low Cost, +2,-2 g Dual Axis Accelerometer with Analog Outputs
MXA2500K Ultra Low Cost, 【1.0 g Dual Axis Accelerometer with Absolute Outputs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MX98726 制造商:MCNIX 制造商全稱(chēng):Macronix International 功能描述:SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE
MX98726AEC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference
MX98726EC 制造商:MCNIX 制造商全稱(chēng):Macronix International 功能描述:SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE
MX98727 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER
MX98728 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*