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參數(shù)資料
| 型號： | MX98715AL |
| 英文描述： | SINGLE CHIP FAST ETHERNET NIC CONTROLLER |
| 中文描述： | 單晶片快速以太網(wǎng)卡控制器 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 215K |
| 代理商： | MX98715AL |
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19
P/N:PM0537
REV. 1.2, FEB. 24, 1999
MX98715A
Field
13
Name
ST
Description
Start/Stop Transmission Command, set to place transmission process in running state
and will try to transmit current descriptor in transmit list. When reset, transmit process is
placed in stop state.
Force Collision Mode, used in collision logic test in internal loopback mode, set to force
collision during next transmission attempt. This can result in excessive collision reported
in TDES0<8> if 16 or more collision.
Loopback Operation Mode, see table 5.2.6.
Full-Duplex Mode, set for simultaneous transmit and receive operation, heart beat check
is disabled, TDES0<7> should be ignored, and internal loopback is not allowed. This bit
controls the value of bit 6 of link code word .
Pass All Multicast, set to accept all incoming frames with a multicast destination address
are received. Incoming frames with physical address are filtered according to the CSR6<0>
bit.
Promiscuous Mode, any incoming valid frames are accepted, default is reset and not
affected by software reset.
Start/Stop Backoff Counter, when reset, the backoff timer is not affected by the network
carrier activity. Otherwise, timer will start counting when carrier drops.
Inverse Filtering, read only bit, set to operate in inverse filtering mode, only valid during
perfect filtering mode.
Pass Bad Frames, set to pass bad frame mode, all incoming frames passed the address
filtering are accepted including runt frames, collided fragments, truncated frames caused
by FIFO overflow.
Hash-Only Filtering Mode , read only bit, set to operate in imperfect filtering mode for both
physical and multicast addresses.
Start/Stop Receive, set to place receive process in running state where descriptor acqui-
sition is attempted from current position in the receive list. Reset to place the receive
process in stop state.
Hash/Perfect Receive Filtering Mode, read only bit, set to use hash table to filter multicast
incoming frames. If CSR6<2> is also set, then the physical addresses are imperfect ad-
dress filtered too. If CSR6<2> is reset, then physical addresses are perfect address fil-
tered, according to a single physical address as specified in setup frame.
12
FC
11:10
9
LOM
FD
7
PM
6
PR
5
SB
4
IF
3
PB
2
HO
1
SR
0
HP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MX98727 | SINGLE CHIP PCI/CARDBUS FAST ETHERNET CONTROLLER |
| MX98742 | FEBC 100 Base Fast Ethernet Bridge Controller |
| MX98902A(PLCC) | LAN Node Controller |
| MX98902A(PQFP) | LAN Node Controller |
| MX98902A(SQFP) | LAN Node Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX98715BEC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:APPLICATION NOTE |
| MX98725 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHERNET NIC CONTROLLER |
| MX98726 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE |
| MX98726AEC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| MX98726EC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE |
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