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參數(shù)資料
| 型號： | MX839 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digitally Controlled Analog I/O Processor |
| 中文描述： | 數(shù)字控制的模擬I / O處理器 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 165K |
| 代理商： | MX839 |
Digitally Controlled Analog I/O Processor
13
MX839 PRELIMINARY INFORMATION
1998 MX
x
COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480164.002
All trademarks and service marks are held by their respective companies.
4.8 Read Only Register Description
4.8.1
IRQ FLAGS Register (Hex Address $D1)
HIRQF1 (Bit 1)
HIRQF2 (Bit 3)
HIRQF3 (Bit 5)
HIRQF4 (Bit 7)
LIRQF1 (Bit 0)
LIRQF2 (Bit 2)
LIRQF3 (Bit 4)
LIRQF4 (Bit 6)
These bits are set if the relevant digital magnitude comparator input exceeds its upper reference level.
These bits are reset to '0' immediately after reading the IRQ FLAGS register. When any of these bits
are set, an interrupt will be generated if the relevant reference level is not zero.
These bits are set if the relevant digital magnitude comparator input falls below its lower reference
level. These bits are reset to '0' immediately after reading the IRQ FLAGS register. When any of
these bits are set, an interrupt will be generated if the relevant reference level is not zero.
Table 9: IRQ FLAGS Register (Hex Address $D1)
4.8.2
A/D DATA1 Register (Hex Address $DC)
4.8.3
A/D DATA2 Register (Hex Address $DD)
4.8.4
A/D DATA3 Register (Hex Address $DE)
4.8.5
This data will consist of two bytes each. Bit 7 to Bit 2 of the second data byte will be set to '0'. Bits 0-7 of the first byte are
the lease significant 8 bits while Bits 0-1 of the second byte are the most significant 2 bits of the 10 bit conversion.
The analog input (V
IN
) is converted to a 10-bit digital word (w) according to:
V
w
DD
The bits of word (w) are returned in 2 bytes as follows:
A/D DATA4 Register (Hex Address $DF)
1024
AV
IN
7
6
5
4
3
2
1
0
Return Byte 1
w
7
0
w
6
0
w
5
0
w
4
0
w
3
0
w
2
0
w
1
w
9
w
0
w
8
Return Byte 2
5 Application
5.1 C-Bus Clock
Although this is specified as a 500kHz clock for compatibility with other C-BUS devices, the MX839 C-BUS will operate
over a much wider range. Users should ensure that the C-BUS clock is at least 4 times slower than the crystal or external
clock on Pin 2 of the MX839.
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