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參數(shù)資料
| 型號： | MX812 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | VSR CODEC WITH DRAM CONTROL |
| 中文描述： | 振動時效編解碼器DRAM的控制 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 115K |
| 代理商： | MX812 |
VSR CODEC with DRAM CONTROL
2
MX812 PRELIMINARY INFORMATION
1997 MX
COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054
Doc. # 20480076.003
All trademarks and service marks are held by their respective companies.
1
CAS:
This output should be connected to the “Column Address Strobe” input pin(s) of all DRAM
devices installed.
2
WE:
This output should be connected to the “Write Enable” input pin(s) of all DRAM devices installed.
3
D:
Digital (speech) data into and out of the VSR Codec. This pin should be connected to the “Data
In” and “Data Out” pins (“D” and “Q”) of DRAM devices.
4
Xtal:
The nominal 4.0MHz clock input to the VSR Codec. The signal applied to this device may be
derived from the attached Audio Processor on-chip Xtal Oscillator circuits (see Figures 2 and 3).
Note
that the VSR Codec will be able to function and maintain correct DRAM refresh, with Xtal input
frequencies down to 2.0MHz. Compand and Local Decoder time constants will change accordingly
and minimum “C-BUS” timings (Figures 6 and 7) would have to be increased pro-rata.
5
Interrupt Request (IRQ):
This Interrupt Request output from the MX812 is ‘wire-OR able’ allowing
the Interrupt Outputs of other peripherals to be commoned and connected to the Interrupt input of the
μ
Processor (see the C-BUS Interface and System Applications document). This input has a low-
impedance pulldown to V
SS
when active, and a high-impedance when inactive.
6
Serial Clock:
The C-BUS serial clock input. This clock produced by the
μ
Controller, is used for
transfer timing of commands and data to and from the VSR Codec. See Timing Diagrams.
7
Command Data:
The C-BUS serial (command) data input from the
μ
Controller. Data is loaded to
this device in 8-bit bytes MSB (B7) first and LSB (B0) last, synchronized to the Serial Clock.
8
Chip Select (CS):
The C-BUS data transfer control function. This input is provided by the
μ
Controller. Transfer sequences are initiated, completed or aborted by this signal. See Timing
Diagrams.
9
Reply Data:
The C-BUS serial data output to the
μ
Controller. The transmission of reply bytes is
synchronized to the Serial Clock under the control of the Chip Select input. This is a 3-state output
which is held at a high-impedance when not sending data to the
μ
Controller.
10
V
:
The output of the internal analog circuitry bias line, held internally at V
DD
/2. This pin should be
decoupled to V
SS
by capacitor C
2
(see Figure 2).
DESCRIPTION
The MX812 is a half-duplex VSR Codec, which
when connected to an audio processing microcircuit
(such as the MX816, 826 or 836), provides the storage
and recovery of speechband audio in attached Dynamic
RAM. The addition of this device will enhance the
communications system by providing cellular radios
with Answering Functions, “Message-Notepad” and
general announcement cababilities.
The MX812 will enable:
Storage of a speech message for transmission
(replay) at a later time.
Storage of a received speech message when the
operator is not attending.
The storage and subsequent replay of speech.
All VSR operating functions are controlled by a
simple serial
μ
Processor interface which may operate
from the radio’s own
μ
Processor/Controller.
Pin
Function
Input audio from the “Store” output of the audio
processor is digitized by delta modulation and stored
via the DRAM controller, in attached memory.
Audio for replay is recovered from the assigned
memory locations and after demodulation made
available for supply to the “Play” input of the audio
processor. For use with other audio systems, the input/
output audio can be connected to relevant points in
circuit.
The MX812 has no on-chip input or output audio
filtering; this capability must therefore be provided by
the host system. Sampling rates and memory capacity
are selectable to 32kb/s or 63kb/s and 1 x 4Mbit or 2 x
1Mbit respectively, which when used in conjunction
allow control of audio-quality and storage-time.
This low-power CMOS device is available 28-pin
plastic SOIC and 28-pin Cerdip packages.
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