(VDD = +5V, VREF
參數(shù)資料
型號： MX7828LP+T
廠商： Maxim Integrated Products
文件頁數(shù)： 6/12頁
文件大?。?/td> 0K
描述： IC ADC 8BIT HS 28-PLCC
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 500
位數(shù)： 8
采樣率（每秒）： 400k
數(shù)據(jù)接口： 并聯(lián)
轉換器數(shù)目： 3
功率耗散（最大）： 75mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 28-LCC（J 形引線）
供應商設備封裝： 28-PLCC（11.51x11.51）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個單端，單極
ELECTRICAL CHARACTERISTICS
(VDD = +5V, VREF+ = +5V, VREF- = GND, Mode 0, TA = TMIN to TMAX, unless otherwise noted.)
TIMING CHARACTERISTICS (Note 5)
(VDD = +5V, VREF+ = +5V, VREF- = GND, Mode 0, TA = TMIN to TMAX, unless otherwise noted.)
Note 1: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 2: Specified with no external load unless otherwise noted.
Note 3: Temperature drift is defined as change in output voltage from +25°C to TMIN or TMAX divided by (25 - TMIN) or (TMAX - 25).
Note 4: Guaranteed by design.
Note 5: All input control signals are specified with tR = tF = 20ns (10% to 90% of +5V) and timed from a 1.6V voltage level.
Note 6: Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7: Defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
_______________________________________________________________________________________
3
(Note 6)
CL = 50pF, RL = 5k
(Note 7)
CL = 50pF
CONDITIONS
ns
60
tDH
Data Hold Time
ns
40
75
tINTH
–
R
—
D
–
to
–
I
—
N
—
T
–
Delay (Mode 1)
ns
0
tCSH
ns
0
tCSS
–
C
—
S
–
to
–
R
—
D
–
Setup Time
–
C
—
S
–
to
–
R
—
D
–
Hold Time
ns
20
50
tACC2
Data Access Time
After
–
I
—
N
—
T
–
, Mode 0
ns
85
tACC1
Data Access Time After
–
R
—
D
–
s
1.6
2.0
tCRD
Conversion Time (Mode 0)
ns
30
40
tRDY
–
C
—
S
–
to RDY Delay
ns
0
tAS
Multiplexer Address
Setup Time
ns
30
tAH
Multiplexer Address
Hold Time
UNITS
TA = +25°C
SYMBOL
PARAMETER
ns
500
tP
Delay Time
Between Conversions
500
70
100
0
60
110
2.4
60
0
35
MAX15_ _C/E
MX782_K/L/B/C
600
70
100
0
70
120
2.8
60
0
40
MAX15_ _M
MX782_T/U
MIN
MAX
MIN
MAX
MIN
TYP
MAX
ns
60
600
tRD
–
R
—
D
–
Pulse Width (Mode 1)
80
500
80
400
DB0–DB7,
–
I
—
N
—
T
–
; IOUT = -360A
–
C
—
S
–
=
–
R
—
D
–
= 2.4V
5V ±5% for specified performance
DB0–DB7, RDY; VOUT = 0V to VDD
VDD = ±5%
CONDITIONS
LSB
±1/16
±1/4
PSS
Power-Supply Sensitivity
V
4.0
VOH
Output High Voltage
mW
25
75
Power Dissipation
mA
15
IDD
Supply Current
V
4.75
5.25
VDD
Supply Voltage
A
±3
Three-State Output Current
pF
58
COUT
Output Capacitance (Note 4)
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
DB0–DB7,
–
I
—
N
—
T
–
; RDY
0.4
V
0.4
VOL
Output Low Voltage
IOUT = 1.6mA
IOUT = 2.6mA
LOGIC OUTPUTS
POWER SUPPLY
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