The VREF+ and V
參數資料
型號: MX7828KCWI+
廠商: Maxim Integrated Products
文件頁數: 11/12頁
文件大小: 0K
描述: IC ADC 8BIT HS 28-SOIC
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 25
位數: 8
采樣率(每秒): 400k
數據接口: 并聯
轉換器數目: 3
功率耗散(最大): 75mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 28-SOIC W
包裝: 管件
輸入數目和類型: 8 個單端,單極
MX7824/MX7828
_____________Analog Considerations
Reference and Input
The VREF+ and VREF- inputs of the converter define the
zero and the full-scale of the ADC. In other words, the
voltage at VREF- is equal to the input voltage that pro-
duces an output code of all zeros, and the voltage at
VREF+ is equal to input voltage that produces an output
code of all ones (Figure 7).
Figure 8 shows some possible reference configura-
tions. For the MAX154/MAX158, a 0.01F bypass
capacitor to GND should be used to reduce the high-
frequency output impedance of the internal reference.
Larger capacitors should not be used, as this degrades
the stability of the reference buffer. The 2.5V reference
output is with respect to the GND pin.
Bypassing
A 47F electrolytic and 0.1F ceramic capacitor should
be used to bypass the VDD pin to GND. These capaci-
tors must have minimum lead length, since excess lead
length may contribute to conversion errors and instability.
If the reference inputs are driven by long lines, they
should be bypassed to GND with 0.1F capacitors at
the reference input pins.
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
8
_______________________________________________________________________________________
DATA
NEW
DATA
ADDR
VALID
INT
RDY
RD
ANALOG
CHANNEL
ADDRESS
CS
tAS
tAH
tRDY
tACCI
tCRD
tRD
tCSS
tRD
tRDY
tINTH
tDH
tAH
tINTH
tAS
tP
tCSS
tCSH
ADDR
VALID
OLD
DATA
tDH
tCSH
tACCI
Figure 6. Mode 1 Timing Diagram
11111111
11111110
11111101
00000011
00000010
00000001
00000000
1
VREF-
23
FS
VREF+
FS–1LSB
OUTPUT
CODE
FULL-SCALE
TRANSITION
1LSB = F8 = VREF+ - VREF-
256
AIN INPUT VOLTAGE
(IN TERMS OF LSBs)
Figure 7. Transfer Function
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