參數(shù)資料
型號(hào): MX574AKEQI+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/18頁
文件大?。?/td> 0K
描述: IC ADC 12BIT W/REF 28-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
位數(shù): 12
采樣率(每秒): 40k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 265mW
電壓電源: 雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極;2 個(gè)單端,雙極
Maxim Integrated Products 10
MAX174/MX574A/MX674A
Industry-Standard, Complete 12-Bit ADCs
Figure 4. Convert Start Timing
Figure 5. Read Timing
Timing and Control
Convert Start Timing—Full Control Mode
R/C must be low before asserting both CE and CS. If it
is high, a brief read operation occurs possibly resulting
in system bus contention. To initiate a conversion, use
either CE or CS. CE is recommended since it is shorter
by one propagation delay than CS and is the faster input
of the two. CE is used to begin the conversion in Figure 4.
The STS output is high during the conversion indicating
the ADC is busy. During this period, additional convert
start commands will be ignored, so that the conversion
cannot be prematurely terminated or restarted. However,
if the state of A0 is changed after the beginning of the
conversion, any additional start conversion transitions
will latch the new state of A0, possibly resulting in an
incorrect conversion length (8 bits vs. 12 bits) for that
conversion.
Read Timing—Full Control Mode
Figure 5 illustrates the read-cycle timing. While reading
data, access time is measured from when CE and R/C
are both high. Access time is extended 10ns if CS is used
to initiate a read.
tHSC
tHEC
CE
A0
STS
D0–D11
tSSC
tHRC
tSRC
tHAC
tDSC
tC
tSAC
HIGH IMPEDANCE
R/C
CS
tSSR
tSRR
tSAR
tHAR
tHRR
tHSR
HIGH IMPEDANCE
tDD
tHD,tHL
CE
A0
STS
D0–D11
R/C
CS
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