參數(shù)資料
型號(hào): MX28F128J3
廠商: Electronic Theatre Controls, Inc.
英文描述: 128M [x8/x16] SINGLE 3V PAGE MODE FLASH MEMORY
中文描述: 128M的[x8/x16]單3V頁(yè)面模式閃存
文件頁(yè)數(shù): 2/6頁(yè)
文件大小: 47K
代理商: MX28F128J3
2
OCT/30/2002
MX28F128J3
GENERAL DESCRIPTION
The MXIC's MX28F128J3 series Flash use the most ad-
vance 2 bits/cell Nbit technology, double the storage ca-
pacity of memory cell. The device provide the high den-
sity Flash memory solution with reliable performance and
most cost-effective.
The device organized as by 8 bits or by 16 bits of output
bus. The device is packaged in 48-Lead TSOP, 48-Lead
RTSOP, 56-Lead TSOP, and 64-ball CSP. It is designed
to be reprogrammed and erased in system or in standard
EPROM programmers.
The device offers fast access time and allowing opera-
tion of high-speed microprocessors without wait states.
To eliminate bus contention, the device has separate chip
enable (CE0, CE1, CE2) and output enable (OE) con-
trols. The device augment EPROM functionality with in-
circuit electrical erasure and programming. The device
uses a command register to manage this functionality.
The MXIC's Nbit technology reliably stores memory con-
tents even after the specific erase and program cycles.
The MXIC cell is designed to optimize the erase and
program mechanisms by utilizing the dielectric's charac-
ter to trap or release charges from ONO layer.
The device uses a 2.7V to 3.6V VCC supply to perform
the High Reliability Erase and auto Program/Erase algo-
rithms.
The highest degree of latch-up protection is achieved
PIN CONFIGURATION
48-TSOP (12mm x 20mm) (for MX28F128J3 word mode only)
WE
A17
A16
A15
A14
A13
A12
A11
A10
A9
A20
A22
A21
A19
A18
A8
A7
A6
A5
A4
A3
A2
A1
CE0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
GND
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
VCC
A23
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
RESET(*)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX28F128J3 (x16 only)
Normal Type
(* RESET pin : high enable)
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