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參數(shù)資料
| 型號(hào)： | MX26L12811MC-12 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 128M [x8/x16] SINGLE 3V PAGE MODE MTP MEMORY |
| 中文描述： | 128M的[x8/x16]單3V頁面模式中期記憶 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大小： | 265K |
| 代理商： | MX26L12811MC-12 |
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11
P/N:PM0990
REV. 1.0, OCT. 29, 2003
MX26L12811MC
High Z
Definition
Symbol When
Status
Notes
Busy
No
Yes
"1"
Ready
"0"
Busy
SR.7
SR.6
WRITE STATE MACHINE STATUS
RESERVED
1
SR.5
Yes
ERASE AND CLEAR LOCK-BITS
STATUS
Error in Block Erasure or
Clear Lock-Bits
Successful Block
Erase or Clear
Lock-Bits
Successful Set Block
Lock Bit
2
SR.4
Yes
PROGRAM AND SET LOCK-BIT
STATUS
PROGRAMMING VOLTAGE
STATUS
Error in Setting Lock-Bit
SR.3
Yes
Low Programming Voltage Programming Voltage
Detected, Operation
Aborted
3
OK
SR.2
Yes
RESERVED
SR.1
Yes
DEVICE PROTECT STATUS
Block Lock-Bit Detected,
Operation Abort
Unlock
4
SR.0
Notes
1. Check STS or SR.7 to determine block erase, program, or lock-bit configuration completion. SR.6-SR.0 are not
driven while SR.7 = 0
2. If both SR.5 and SR.4 are "1" after a block erase or lock-bit configuration attempt, an improper command se-
quence was entered.
3. SR.3 does not provide a continuous programming voltage level indication. The WSM interrogates and indicates the
programming voltage level only after Block Erase, Program, Set Block Lock-Bit, or Clear Block Lock-Bits com-
mand sequences.
4. SR.1 does not provide a continuous indication of block lock-bit values. The WSM interrogates the block lock-bits
only after Block Erase, Program, or Lock-Bit configuration command sequences. It informs the system, depend-
ing on the attempted operation, if the block lock-bit is set. Read the block lock configuration codes using the Read
Identifier Codes command to determine block lock-bit status.
5. SR.0 is reserved for future use and should be masked when polling the status register.
Yes
RESERVED
5
Table 4. Status Register Definitions
High Z
Definition
Symbol When
Status
Notes
Busy
No
Yes
"1"
Write buffer available
"0"
Write buffer not available
XSR.7
XSR.6-
XSR.0
WRITE BUFFER STATUS
RESERVED
1
2
Table 5. Extended Status Register Definitions
Notes:
1. After a Buffer-Write command, XSR.7 = 1 indicates that a Write Buffer is available.
2. XSR.6-XSR.0 are reserved for future use and should be masked when polling the status register.
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| MX26L1620 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:16M-BIT [1M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
| MX26L1620MC-12 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:16M-BIT [1M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
| MX26L1620MC-90 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:16M-BIT [1M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
| MX26L1620MI-12 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:16M-BIT [1M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
| MX26L1620MI-90 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:16M-BIT [1M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM |
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