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參數(shù)資料
| 型號： | MX10EXAUI |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, LQFP-44 |
| 文件頁數(shù)： | 16/55頁 |
| 文件大?。?/td> | 476K |
| 代理商： | MX10EXAUI |
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P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005
MX10EXA
PT1
PT0
OPERATING
Prescaler selection.
0
Osc/4
0
1
Osc/16
1
0
Osc/64
1
Reserved
CM
Compatibility Mode allows the XA to execute most translated 80C51 code on the XA. The
XA register file must copy the 80C51 mapping to data memory and mimic the 80C51
indirect addressing scheme.
PZ
Page Zero mode forces all program and data addresses to 16-bits only. This saves stack
space and speeds up execution but limits memory access to 64k.
Figure 5. System Configuration Register (SCR)
GATE
Gating control when set. Timer/Counter "n" is enabled only while "INTn" pin is high and "TRn"
control bit is set. When cleared Timer "n" is enabled whenever "TRn" control bit is set.
C/T
Timer or Counter Selector cleared for Timer operation (input from internal system clock.) Set for
Counter operation (input from "Tn" input pin).
M1
M0
OPERATING
0
16-bit auto-reload timer/counter
0
1
16-bit non-auto-reload timer/counter
1
0
8-bit auto-reload timer/counter
1
Dual 8-bit timer mode (timer 0 only)
Figure 6. Timer/Counter Mode Control (TMOD) Register
-
PT1
MSB
LSB
PT0
CM
PZ
Not Bit Addressable
Reset Value:00H
-
SCR
Address:440
GATE
C/T
TIMER 1
TIMER 0
M1
M0
GATE
MSB
LSB
C/T
M1
M0
Not Bit Addressable
Reset Value:00H
Address:45C
TMOD
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