參數(shù)資料
型號(hào)： MX10EXAQI
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 31/55頁(yè)
文件大小： 476K
代理商： MX10EXAQI
37
P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005
MX10EXA
Where SM0, SM1, specify the serial port mode, as bollows:
SM0
SM1
Mode
Description
Baud Rate
0
shift register
f
OSC/16
0
1
8-bit UART
variable
1
0
2
9-bit UART
f
OSC/32
1
3
9-bit UART
variable
BIT
SYMBOL
FUNCTION
SnCON.5
SM2
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or
3, if SM2 is set to 1, then RI will not be activated it the received 9th data bit (RB8)
is 0. In Mode 1, it SM2=1 then RI will not be activated if a valid stop bit was not
received. In Mode 0, SM2 should be 0.
SnCON.4
REN
Enables serial reception. Set by software to enable reception. Clear by software to
disable reception.
SnCON.3
TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software
as desired. The TB8 bit is not double buffered. See text for details.
SnCON.2
RB8
In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8
is the stop bit that was received. In Mode 0, RB8 is not used.
SnCON.1
TI
Transmit interrupt flag. Set when another byte may be written to the UART transmit-
ter. See text for details. Must be cleared by software.
SnCON.0
RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
at the end of the stop bit time in the other modes (except see SM2). Must be
cleared by software.
SM0
SM1
SM2
REN
TB8
MSB
LSB
RB8
TI
RI
Bit Addressable
Reset Value:00H
SnCON
Address:S0CON 420
S1CON 424
Figure 16. Serial Port Control (SnCON) Register
STINTn SnSTAT
If 0, sets FE
OEn
BRn
FEn
-
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
ONLY IN
MODE 2,3
DATA BYTE
STOP
BIT
Figure 17. UART Framing Error Detection
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