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參數(shù)資料
| 型號(hào)： | MWS5101ELS |
| 廠商： | INTERSIL CORP |
| 元件分類： | Static RAM |
| 英文描述： | 256 X 4 STANDARD SRAM, 350 ns, PDIP22 |
| 封裝： | PLASTIC, DIP-22 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大小： | 142K |
| 代理商： | MWS5101ELS |
59
Dynamic Electrical Specifications at TA = 0oC to +70oC, VDD = 5V ±5%
PARAMETER
SYMBOL
LIMITS (NOTE 1)
UNITS
L2 TYPES
L3 TYPES
(NOTE 2)
MIN
(NOTE 3)
TYP
MAX
(NOTE 2)
MIN
(NOTE 3)
TYP
MAX
READ CYCLE TIMES (FIGURE 1)
Read Cycle
tRC
250
-
350
-
ns
Access from Address
tAA
-
150
250
-
200
350
ns
Output Valid from Chip Select 1tDOA1
-
150
250
-
200
350
ns
Output Valid from Chip Select 2
tDOA2
-
150
250
-
200
350
ns
Output Valid from Output Disable
tDOA3
-
110
-
150
ns
Output Hold from Chip Select 1tDOH1
20
-
20
-
ns
Output Hold from Chip Select 2
tDOH2
20
-
20
-
ns
Output Hold from Output Disable
tDOH3
20
-
20
-
ns
WRITE CYCLE TIMES (FIGURE 2)
Write Cycle
tWC
300
-
400
-
ns
Address Setup
tAS
110
-
150
-
ns
Write Recovery
tWR
40
-
50
-
ns
Write Width
tWRW
150
-
200
-
ns
Input Data Setup Time
tDS
150
-
200
-
ns
Data in Hold
tDH
40
-
50
-
ns
Chip Select 1 Setup
tCS1S
110
-
150
-
ns
Chip Select 2 Setup
tCS2S
110
-
150
-
ns
Chip Select 1 Hold
tCS1H
0-
-
0
-
ns
Chip Select 2 Hold
tCS2H
0-
-
0
-
ns
Output Disable Setup
tODS
110
-
150
-
ns
NOTES:
1. MWS5101: tR, tF = 20ns, VIH = 0.7VDD, VIL = 0.3VDD; CL = 100pF and MWS5101A: tR, tF = 20ns, VIH = 2.2V, VIL = 0.65V; CL = 50pF
and 1 TTL Load.
2. Time required by a limit device to allow for the indicated function.
3. Typical values are for TA = 25
oC and nominal V
DD.
MWS5101, MWS5101A
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