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參數(shù)資料
| 型號： | MVTX2804AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 8-Port 1000 Mbps Ethernet Distributed Switch |
| 中文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA596 |
| 封裝： | 40 X 40 MM, 2.33 MM HEIGHT, MS-034, HSBGA-596 |
| 文件頁數(shù)： | 16/174頁 |
| 文件大?。?/td> | 2249K |
| 代理商： | MVTX2804AG |
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MVTX2804
Data Sheet
16
Zarlink Semiconductor Inc.
1.0 Block Functionality
1.1 Frame Data Buffer (FDB) Interfaces
The FDB interface supports pipelined ZBT-SRAM memory at 133 MHz. To ensure a non-blocking switch, two
memory domains are required. Each domain has a 64-bit wide memory bus. At 133 MHz, the aggregate
memory bandwidth is 17 Gbps, which is enough to support 8 Gigabit ports at full wire speed switching. A patent
pending scheme is used to access the FDB memory. Each slot has one tick to read or write 8 bytes.
1.2 Switch Database (SDB) Interface
A pipelined synchronous burst SRAM (SBRAM) memory is used to store the switch database information
including MAC Table, VLAN Table and IP Multicast Table. Search Engine accesses the switch database via
SDB interface. The SDB memory has 32-bit wide bus at 133MHz.
1.3 GMII/PCS MAC Module (GMAC)
The GMII/PCS Media Access Control (MAC) module provides the necessary buffers and control interface
between the Frame Engine (FE) and the external physical device (PHY). The MVTX2804 has two interfaces,
GMII or PCS. The MAC of the MVTX2804 meets the IEEE 802.3z specification and supports the MII interface. It
is able to operate in 10M/100M/1G in Full Duplex mode with a flow control mechanism. It has the options to
insert Source Address/CRC/VLAN ID to each frame. The GMII/PCS Module also supports hot plug detection.
1.4 CPU Interface Module
One extra port is dedicated to the CPU via the CPU interface module. The CPU interface utilizes a 16/8-bit bus
in managed mode. It also supports a serial and an I
2
C interface, which provides an easy way to configure the
system if unmanaged.
1.5 Management Module
The CPU can send a control frame to access or configure the internal network management database. The
Management Module decodes the control frame and executes the functions requested by the CPU.
1.6 Frame Engine
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame
arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, which is sent
to the search engine to resolve the destination port. The arriving frame is moved to the FDB. After receiving a
switch response from the search engine, the frame engine performs transmission scheduling based on the
frame's priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
1.7 Search Engine
The Search Engine resolves the frame's destination port or ports according to the destination MAC address (L2)
or IP multicast address (IP multicast packet) by searching the database. It also performs MAC learning, priority
assignment, and trunking functions.
1.8 LED Interface
The LED interface can be operated in a serial mode or a parallel mode. In the serial mode, the LED interface
uses 3 pins for carrying 8 port status signals. In the parallel mode, the interface can drive LEDs by 8 status pins.
The LED port is shared with bootstrap pins. In order to avoid mis-reading a buffer must be used to isolate the
LED circuitry from the bootstrap pins during bootstrap cycle (the bootstraps are sampled at the rising edge of
the #Reset).
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