參數(shù)資料
型號： MVTX2602
廠商： Zarlink Semiconductor Inc.
英文描述： Managed 24 Port 10/100 Mbps Ethernet Switch
中文描述： 管理的24端口10/100 Mbps以太網(wǎng)交換機
文件頁數(shù)： 94/147頁
文件大?。?/td> 924K
代理商： MVTX2602
MVTX2602
Data Sheet
94
Zarlink Semiconductor Inc.
Their respective priority can be programmed via Well_Known_Port [7:0] priority register. Well_Known_Port_ Enable
can individually turn on/off each Well Known Port if desired.
Similarly, the User Defined Logical Port provides the user programmability to the priority plus the flexibility to select
specific logical ports to fit the applications. The 8 User Logical Ports can be programmed via User_Port 0-7
registers. Two registers are required to be programmed for the logical port number. The respective priority can be
programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via
User_Port_Enable register.
The User Defined Range provides a range of logical port numbers with the same priority level. Programming is
similar to the User Defined Logical Port. Instead of programming a fixed port number, an upper and lower limit need
to be programmed, they are: {RHIGHH, RHIGHL} and {RLOWH, RLOWL} respectively. If the value in the upper limit
is smaller or equal to the lower limit, the function is disabled. Any IP packet with a logical port that is less than the
upper limit and more than the lower limit will use the priority specified in RPRIORITY.
13.6.34 USER_PORT0_(0~7) – User Define Logical Port (0~7)
USER_PORT_0 - I2C Address h0D6 + h0DE; CPU Address 580(Low) + 581(high)
USER_PORT_1 - I2C Address h0D7 + h0DF; CPU Address 582 + 583
USER_PORT_2 - I2C Address h0D8 + h0E0; CPU Address 584 + 585
USER_PORT_3 - I2C Address h0D9 + h0E1; CPU Address 586 + 587
USER_PORT_4 - I2C Address h0DA + h0E2; CPU Address 588 + 589
USER_PORT_5 - I2C Address h0DB + h0E3; CPU Address 58A + 58B
USER_PORT_6 - I2C Address h0DC + h0E4; CPU Address 58C + 58D
USER_PORT_7 - I2C Address h0DD + h0E5; CPU Address 58E + 58F
Accessed by CPU, serial interface and I2C (R/W)
(Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the CPU to define
eight separate ports.
13.6.35 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority
I2C Address h0E6, CPU Address h590
Accessed by CPU, serial interface and I2C (R/W)
7
0
TCP/UDP Logic Port Low
7
0
TCP/UDP Logic Port High
7
5
4
3
1
0
Priority 1
Drop
Priority 0
Drop
相關(guān)PDF資料
PDF描述
MVTX2602AG Managed 24 Port 10/100 Mbps Ethernet Switch
MVTX2603 Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch
MVTX2603AG Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch
MVTX2604 Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch
MVTX2604AG Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MVTX2602A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MVTX260x Port Mirroring
MVTX2602AG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 24 Port 10/100 Mbps Ethernet Switch
MVTX2602AG2 制造商:Microsemi Corporation 功能描述:
MVTX2603 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch
MVTX2603A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Unmanaged 24 port 10/100Mb + 2 port 1Gb Ethernet switch
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