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MVTX1100
Data Sheet
31
Zarlink Semiconductor Inc.
13.1 STRAP Options
The Strap options are relevant during the initial power-on period, when reset is asserted. During reset, MVTX1100
will examine the boot strap address pin to determine its value and modify the internal configuration of the chip
accordingly.
“1” means Pull Up
“0” means Pull Down with an external 1 K Ohm
Default value is 1, (all boot strap pins have internal pull up resistor).
Note 1:
1. If the MVTX1100 is configured from EEPROM preset (L_A[6] pulled down at reset), it will try to load its configuration from
the EEPROM. If the EEPROM is blank or not preset, it will not boot up. The parallel port can be used to program the EEPROM
at any time.
Note 2:
During normal power-up the MVTX1100 will run through an external SBRAM memory test to ensure that there are no memory
interface problems. If a problem is detected, the chip will stop functioning. To facilitate board debug in the event that a system
stops functioning, the MVTX1100 can be put into a continuous SBRAM self test mode to allow an operator to determine if
there are stuck pins in the memory interface (using network analyzer).
Pin No(s)
Symbol
Name & Functions
206 (L_A[5])
Memory Size
1 - Memory size = 256 KB,
0 - Memory size = 512 KB
1 - NO EEPROM Installed
0 - EEPROM Installed
1
1 - Enable
0 - Disable
11 - 100 Mbps
10 - 200 Mbps
01 - 300 Mbps
00 - 400 Mbps (0 - Pull down, 1 - Pull up)
1 - RMII Mode for ports 0-7
0 - Serial mode for ports 0-7
1 - MII Mode for port 8
0 - Serial mode for port 8
Link Polarity for serial interface
1 - Active Low
0 - Active High
Full/Half Duplex Polarity for serial interface
1 - Active Low
0 - Active High
Speed polarity for serial interface
1 - Active Low
0 - Active High
Use in cascade mode only
For Board/System Manufacturing Test
2
1 - Disable
0 - Enable
208 (L_A [6])
EEPROM
1 (L_A [7])
MII Management
via MDIO
XLINK Speed
5, 4 (L_A [10:9])
160 (L_A[15])
151 (L_A[17])
Ports 0-7 RMII/Serial
Port 8 MII/Serial
150 (L_A[2])
Link Polarity
204 (L_A[3])
FDX Polarity
205 (L_A[4])
SPD100 Polarity
2 (L_A[8])
133 (TST[2])
Device ID
SBRAM Self Test