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參數(shù)資料
| 型號(hào)： | MVME147-024 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Single-board computer |
| 中文描述： | 單板計(jì)算機(jī) |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 178K |
| 代理商： | MVME147-024 |
MVME6000
VMEbus
Interface
EPROM
4 Sockets
2 Banks
MC68030
MPU
GCC
ASIC
4 to 32MB
DRAM Memory
Array with Parity
LXT901
Serial
Interface
Adapter
Centronics
Printer
Interface
AM7990
Ethernet
Transceiver
MC68882
FPC
33C93
SCSI
Interface
Adapter
8530
Serial
Controller
(two)
PCC
ASIC
M48T18
Battery-Backed
4KB NVRAM/Clock
MVME147 Block Diagram
Performance
16 MHz
25 MHz
33.33 MHz
Access Sequence
MPU to Local DRAM
No Parity
Delayed Parity
Parity
MPU to Local ROM
VMEbus to Local DRAM
Read Cycles
Write Cycles
Read Cycles
Write Cycles
Read Cycles
Write Cycles
Notes
4
4
4
4
5
13
13
4
4
4
13
11
4
4
5
16
13
4
4
4
16
11
1, 2
1, 2
1, 2
1, 3
4, 5
N/A
N/A
9
13
813ns
N/A
N/A
9
11
688ns
520ns
440ns
390ns
330ns
MPU to Global RAM
VMEbus Master
System Controller/Not Master
Not System Controller/Not Master
Notes:
1.
No arbitration overhead.
2.
Except RMW cycles where the MVME147 is required to obtain VMEbus mastership before RMW cycle can be started.
3.
Device access time must be 200ns or less.
4.
DS0*/DS1* asserted to DTACK* asserted.
5.
Typical values. Actual values may be greater or less depending on the state of the slave device.
6.
A = ta/T cycles.
7.
B = (ta + tr)/T cycles.
8.
C = (ta + tg)/T cycles.
6 + A
11 + B
9 + C
6 + A
11 + B
9 + C
9 + A
17 + B
15 + C
9 + A
17 + B
15 + C
12 + A
22 + B
19 + C
12 + A
22 + B
19 + C
5, 6
5, 7
5, 8
ta = DS0*/DS1* to the assertion of DTACK* (slave access time).
tr = Brx* low to BBSY high and AS* high (bus requested and granted).
tg = Brx* low to BGINx* low and AS* high (bus requested and granted).
T = MPU clock period, 16 MHz = 62.5 ns, 25 MHz = 40 ns, 33.33 MHz = 30 ns.
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