參數(shù)資料
型號(hào)： MUAA8K80M-20B388C
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 9/24頁(yè)
文件大?。?/td> 395K
代理商： MUAA8K80M-20B388C
Operational Characteristics
MUAA Routing CoProcessor (RCP) Family
Rev. 3
9
Operations
On the synchronous port, operations are started on the
CLK cycle in which the requested Op-Code is written. On
the processor port operations are started when the chosen
operation register is written. The user should use the flow
control mechanisms to determine when results are
available. On the synchronous port the /DOUTVALID
signal is asserted for one CLK cycle when new data is
written to the DOUT port. The processor port will assert
its PROCREADY signal on the CLK edge that data is
available. Note that there is no internal flow control from
the sync DOUT port back to the sync DIN port. The
DOUT data is overwritten if it is not unloaded.
Note:
*Bus bits [15:0] contain data. Bus bits [31:16] are undefined.
Device Chaining
Up to four MUAA 2K RCPs may be chained with no
external logic. Figure 3 shows the interconnection. Unused
CHAIN[3:0] pins should be left unconnected.
The /MF, /FF, INT, DOUTVALID, DINREADY, and
PROCREADY signals should only be used on the master
device and left disconnected on the slave devices. The
master device is the one with no connection to the
CHAINUP pin.
Where device pins are paralleled, attention should be paid
to signal integrity, in particular to signals used for
clocking, i.e., CLK, /PCS. PCB layout techniques such as
daisy chaining and driver to track impedance matching
should be observed.
The scheme in Figure 3 allows devices to be designed in
but not fitted. The fit order would be MASTER, SLAVE1,
SLAVE2, SLAVE3.
Table 2: 32-Bit Bus Mode CAM/RAM Cycles by Partition Configuration
Cycle
1
2
3
No RAM 79:0 CAM
CAM[31:0]
CAM[63:32]
CAM[79:64]*
79:64 RAM 63:0 CAM
CAM[31:0]
CAM[63:32]
RAM[79:64]*
79:48 RAM 47:0 CAM
CAM[31:0]
CAM[47:32]*
RAM[79:48]
79:32 RAM 31:0 CAM
CAM[31:0]
RAM[63:32]
RAM[79:64]*
Table 3: 16-Bit Bus Mode CAM/RAM Cycles by Partition Configuration
Cycle
1
2
3
4
5
No RAM 79:0 CAM
CAM[15:0]
CAM[31:16]
CAM[47:32]
CAM[63:48]
CAM[79:64]
79:64 RAM 63:0 CAM
CAM[15:0]
CAM[31:16]
CAM[47:32]
CAM[63:48]
RAM[79:64]
79:48 RAM 47:0 CAM
CAM[15:0]
CAM[31:16]
CAM[47:32]
RAM[63:48]
RAM[79:64]
79:32 RAM 31:0 CAM
CAM[15:0]
CAM[31:16]
RAM[47:32]
RAM[63:48]
RAM[79:64]
Table 4: Input and Output CAM/RAM Cycles by Operation
Operation
INSERT
SEARCH
SEARCHA
LEARN
DELETE
READ LQUEUE
READ AQUEUE
DIN, PROCD (Write)
CAM & RAM
CAM only
CAM only
CAM & RAM
CAM only
N/A
N/A
DOUT, PROCD (Read)
N/A
RAM only
RAM only
N/A
N/A
CAM & RAM
CAM & RAM
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